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From: Conor Dooley <conor@kernel.org>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: "Srinivas Kandagatla" <srini@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	"Alim Akhtar" <alim.akhtar@samsung.com>,
	"Peter Griffin" <peter.griffin@linaro.org>,
	"André Draszik" <andre.draszik@linaro.org>,
	semen.protsenko@linaro.org, willmcvicker@google.com,
	kernel-team@android.com, linux-kernel@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/5] dt-bindings: nvmem: add google,gs101-otp
Date: Fri, 31 Oct 2025 15:02:01 +0000	[thread overview]
Message-ID: <20251031-seltzer-briskness-6f223654c993@spud> (raw)
In-Reply-To: <20251031-gs101-otp-v1-1-2a54f6c4e7b6@linaro.org>

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On Fri, Oct 31, 2025 at 12:45:09PM +0000, Tudor Ambarus wrote:
> Add binding for the OTP controller found on Google GS101.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> ---
>  .../bindings/nvmem/google,gs101-otp.yaml           | 68 ++++++++++++++++++++++
>  1 file changed, 68 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml b/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..2144911297beb89337b0389b30fe6609db4156ea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/google,gs101-otp.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/nvmem/google,gs101-otp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 OTP Controller
> +
> +maintainers:
> +  - Tudor Ambarus <tudor.ambarus@linaro.org>
> +
> +description: |
> +  OTP controller drives a NVMEM memory where system or user specific data
> +  can be stored. The OTP controller register space if of interest as well
> +  because it contains dedicated registers where it stores the Product ID
> +  and the Chip ID (apart other things like TMU or ASV info).
> +
> +allOf:
> +  - $ref: nvmem.yaml#
> +  - $ref: nvmem-deprecated-cells.yaml

Why are the deprecated cells needed here?
|  Before introducing NVMEM layouts all NVMEM (fixed) cells were defined
|  as direct device subnodes. That syntax was replaced by "fixed-layout"
|  and is deprecated now. No new bindings should use it.

> +
> +properties:
> +  compatible:
> +    items:
> +      - const: google,gs101-otp
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: pclk

Why bother with clock-names when you only have one clock? Are you
anticipating a variant with more?

> +
> +  reg:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#address-cells"
> +  - "#size-cells"
> +  - clock-names
> +  - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/google,gs101.h>
> +
> +    otp: efuse@10000000 {
> +        compatible = "google,gs101-otp";
> +        reg = <0x10000000 0xf084>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>;
> +        clock-names = "pclk";
> +
> +        product_id: product_id@0 {

Why does this node name have an underscore?

Additionally, all nodes here should lose their labels.

pw-bot: changes-requested

> +            reg = <0x0 0x4>;
> +        };
> +
> +        chip_id: chip-id@4 {
> +            reg = <0x4 0x10>;
> +        };
> +    };
> 
> -- 
> 2.51.1.930.gacf6e81ea2-goog
> 

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  reply	other threads:[~2025-10-31 15:02 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-31 12:45 [PATCH 0/5] nvmem: add Samsung Exynos OTP support Tudor Ambarus
2025-10-31 12:45 ` [PATCH 1/5] dt-bindings: nvmem: add google,gs101-otp Tudor Ambarus
2025-10-31 15:02   ` Conor Dooley [this message]
2025-10-31 16:06     ` Tudor Ambarus
2025-10-31 12:45 ` [PATCH 2/5] nvmem: add Samsung Exynos OTP support Tudor Ambarus
2025-11-04  7:19   ` Krzysztof Kozlowski
2025-11-10  9:52     ` Tudor Ambarus
2025-10-31 12:45 ` [PATCH 3/5] arm64: dts: exynos: gs101: add OTP node Tudor Ambarus
2025-10-31 12:45 ` [PATCH 4/5] arm64: defconfig: enable Samsung Exynos OTP controller Tudor Ambarus
2025-10-31 12:45 ` [PATCH 5/5] MAINTAINERS: add entry for the Samsung Exynos OTP controller driver Tudor Ambarus

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