Re: [PATCH v3 0/4] Add i.MX95 USB3.0 PHY alternate clock support

[Peng Fan <peng.fan@oss.nxp.com>]

Hi Xu,

On Mon, Nov 03, 2025 at 06:08:31PM +0800, Xu Yang wrote:
>The i.MX95 USB3.0 PHY supports XTAL 24MHz clock by default as reference
>clock and 100MHz clock as alternate reference clock. If the default
>reference clock brings USB performance degradation in bad condition, such
>as the working temperature is too low or too high, switch to alternate
>clock may overcome the degradation. This will add alternate clock support
>to enhance the function of USB3.0 PHY.

I gave a recheck on this patchset. Sorry, need to take back my R-b from patch 3.
I think we need to avoid introduce xx-usb-blk-ctl here.

Reuse imx95 hsio-blk-ctl and fix that node.

We only have one HSIO BLK CTRL, PCIE(0xc0) and USB(0x00) both should use it,
but not introduce a new compatible.

Let me give a look on current BLK CTRL for PCIE stuff and extend it to support
USB.

Thanks,
Peng

>
>---
>Changes in v3:
>- collect some Rb and Ab tag
>- Link to v2: https://lore.kernel.org/r/20251010-usb-phy-alt-clk-support-v2-0-af4b78bb4ae8@nxp.com
>
>Changes in v2:
>- improve patch #1 commit message
>- collect Rb tag
>- Link to v1: https://lore.kernel.org/r/20250919-usb-phy-alt-clk-support-v1-0-57c2a13eea1c@nxp.com
>
>---
>Xu Yang (4):
>      dt-bindings: phy: imx8mq-usb: add alternate reference clock
>      dt-bindings: clock: nxp,imx95-blk-ctl: add support for USB in HSIO Block Control
>      phy: fsl-imx8mq-usb: support alternate reference clock
>      clk: imx95-blk-ctl: Add one clock mux for HSIO block
>
> .../bindings/clock/nxp,imx95-blk-ctl.yaml          |  1 +
> .../bindings/phy/fsl,imx8mq-usb-phy.yaml           |  7 ++++++-
> drivers/clk/imx/clk-imx95-blk-ctl.c                | 19 ++++++++++++++++++
> drivers/phy/freescale/phy-fsl-imx8mq-usb.c         | 23 ++++++++++++++++++++--
> 4 files changed, 47 insertions(+), 3 deletions(-)
>---
>base-commit: 18514fd70ea4ca9de137bb3bceeac1bac4bcad75
>change-id: 20250919-usb-phy-alt-clk-support-e54e69ac0780
>
>Best regards,
>-- 
>Xu Yang <xu.yang_2@nxp.com>
>