From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D552D257827 for ; Sun, 16 Nov 2025 20:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763326123; cv=none; b=GI1sWogNYUOxAfzGvcIygYf/YTyDz7IRYkS3NPp8SSgg401LlxI/bd5hVBe0J9PcKoWmJKXnKW/ZXVa9TODiTal17Lw7DLUn1WaVBbyeypp2+uqQ06gbSsqMDl/5XEW22kXuA9S/Klw3YvjIGwxDLPPH7spq+VLhso1dW1dyxTg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763326123; c=relaxed/simple; bh=tAS/jFdleKntCdfZ4fDFe0Ru8lUvDl2di+Bd5ceHE8Q=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=on3zTdTXXDvZcpxO9eTPmqjgLcDjiqteaB5/9c3wTKWbpdAs6SSP6xBOADnoBmcusbi0OCQty5rv6NN5ohGnEHXSUlX+z61XoKyo16Swqy+ZDhhFRyTP4Nf8T4kEXVE47ODKGSghGcGW362YqlVG1wOVtOo7MWzlYvpKT1FZRfo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DKeGhdMX; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HpmpZHMr; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DKeGhdMX"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HpmpZHMr" Message-ID: <20251104075426.796873498@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1763326120; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=t2DhrCJI2qM1WXFN4uYMENxUwcTd/AJvvwXrw8JDNI8=; b=DKeGhdMXf6gy/8ZmgLgNZdPA9MSDN4T9Dp9jlZWtDm5l4a4VY1khIF5kIOogj1goTDHNSR 4OMAzFSFzjbJGOHfCMLlncr6shCc/IzDsRVr6zPIYByesJWqSbwBkSRKZ960XUeYca+2Lo d2B3Su2FL0khPjRa991ArAYgI+ICE6gJcgAFKjNyij5coJdLKow5bbk1jn/QaGbc5fDRCk 7euOpNzI2+k1YsFU+8XsD2Lu33nh3jUz+IJXmbmRDpyd2AZK5T/Y3WbTn+b6vCJmshdZJq oydoJpfOfLa70KoVqwBEWwvCYE7ua9KQ47aijDiLDbj1dHGsbgwVrQZsOMA8YQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1763326120; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=t2DhrCJI2qM1WXFN4uYMENxUwcTd/AJvvwXrw8JDNI8=; b=HpmpZHMr4YuFRzQKtZBguhH1c+ZUFA5ArT+X7dyIkT2nR3zLmfpAPCPlHN7zgl6OVPpn+L zPAl8dZIKqb4GqAw== From: Thomas Gleixner To: LKML Cc: Peter Zijlstra , Gabriele Monaco , Mathieu Desnoyers , Michael Jeanson , Jens Axboe , "Paul E. McKenney" , "Gautham R. Shenoy" , Florian Weimer , Tim Chen , Yury Norov , Shrikanth Hegde Subject: [patch V4 03/20] sched/mmcid: Cacheline align MM CID storage References: <20251104075053.700034556@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Date: Sun, 16 Nov 2025 21:48:39 +0100 (CET) Both the per CPU storage and the data in mm_struct are heavily used in context switch. As they can end up next to other frequently modified data, they are subject to false sharing. Make them cache line aligned. Signed-off-by: Thomas Gleixner --- include/linux/rseq_types.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/include/linux/rseq_types.h +++ b/include/linux/rseq_types.h @@ -112,7 +112,7 @@ struct sched_mm_cid { */ struct mm_cid_pcpu { unsigned int cid; -}; +}____cacheline_aligned_in_smp; /** * struct mm_mm_cid - Storage for per MM CID data @@ -126,7 +126,7 @@ struct mm_mm_cid { struct mm_cid_pcpu __percpu *pcpu; unsigned int nr_cpus_allowed; raw_spinlock_t lock; -}; +}____cacheline_aligned_in_smp; #else /* CONFIG_SCHED_MM_CID */ struct mm_mm_cid { }; struct sched_mm_cid { };