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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2025 08:36:59.3662 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0211769e-7ba8-4e43-9213-08de1b7d5212 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF84B7B0C96 Thanks to "drm/ttm: rework pipelined eviction fence handling", ttm can deal correctly with moves and evictions being executed from different contexts. Create several entities and use them in a round-robin fashion. Signed-off-by: Pierre-Eric Pelloux-Prayer --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 +++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 839ea8c7f6be..c3a88574f143 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -401,6 +401,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); + struct amdgpu_ttm_entity *entity; struct amdgpu_copy_mem src, dst; struct dma_fence *fence = NULL; int r; @@ -412,8 +413,12 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, src.offset = 0; dst.offset = 0; + int e = atomic_inc_return(&adev->mman.next_move_entity) % + adev->mman.num_move_entities; + entity = &adev->mman.move_entities[e]; + r = amdgpu_ttm_copy_mem_to_mem(adev, - &adev->mman.move_entities[0], + entity, &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), @@ -426,7 +431,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence = NULL; - r = amdgpu_fill_buffer(&adev->mman.move_entities[0], + r = amdgpu_fill_buffer(entity, abo, 0, &wipe_fence, fence, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { @@ -2179,10 +2184,12 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); uint64_t size; int r, i, j; - u32 num_clear_entities, num_move_entities, windows, w; + u32 num_clear_entities, num_move_entities; + u32 windows, w; num_clear_entities = adev->sdma.num_instances; num_move_entities = MIN(adev->sdma.num_instances, TTM_FENCES_MAX_SLOT_COUNT); + man->pipelined_eviction.n_fences = num_move_entities; windows = adev->gmc.is_app_apu ? 0 : (2 * num_move_entities + num_clear_entities); if (!adev->mman.initialized || amdgpu_in_reset(adev) || @@ -2205,6 +2212,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) } adev->mman.num_move_entities = num_move_entities; + atomic_set(&adev->mman.next_move_entity, 0); for (i = 0; i < num_move_entities; i++) { r = drm_sched_entity_init(&adev->mman.move_entities[i].base, DRM_SCHED_PRIORITY_NORMAL, &sched, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 3fc31c7c6bfe..c3df9d24fb96 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -76,6 +76,7 @@ struct amdgpu_mman { atomic_t next_clear_entity; u32 num_clear_entities; struct amdgpu_ttm_entity move_entities[TTM_FENCES_MAX_SLOT_COUNT]; + atomic_t next_move_entity; u32 num_move_entities; struct amdgpu_vram_mgr vram_mgr; -- 2.43.0