[PATCH v7 0/2] Adjust bandwidth limit for DP

[Liankun Yang <liankun.yang@mediatek.com>]

DP link training checks the current PHY link signal quality.
After DP detects an HPD connection, it should first determine
the current link signal quality in order to select the resolution.

Since the EDP is already fixed to use the EDP panel,
the current training information and resolution are basically fixed.
EDP exists and its process differs from DP. Therefore,
it is necessary to isolate the parsing capability,
panel power, training state and enable state.

For example, the platform support DP 4lane 5.4G,
but panel A support DP 2lane 5.4G.

This is a time sequence:

1. Plug in panel A. According to the platform, it can output 4K 60Hz.
2. Timing mode set 4K 60Hz.
3. Atomic enable(Based on panel A ability, training pass 2lane 5.4G).
4. Finally, due to 2lane 5.4G bandwidth limitation, the platform cannot
output 4K 60Hz, resulting in a black sreen.

If apply this patch.

1. Plug in panel A.
2. Training pass 2lane 5.4G
3. Timing mode set 2K 60Hz(Based on the 2lane 5.4G bandwidth limit).
4. Atomic enable for output screen.

Liankun Yang (2):
  drm/mediatek: Adjust bandwidth limit for DP
  drm/mediatek: Add isolation to edp

 drivers/gpu/drm/mediatek/mtk_dp.c | 57 ++++++++++++++++++++-----------
 1 file changed, 38 insertions(+), 19 deletions(-)

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2.45.2