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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF000026C5.mail.protection.outlook.com (10.167.244.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.13 via Frontend Transport; Wed, 12 Nov 2025 18:25:29 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 12 Nov 2025 10:25:22 -0800 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v5 00/14] iommu/amd: Introduce Nested Translation support Date: Wed, 12 Nov 2025 18:24:52 +0000 Message-ID: <20251112182506.7165-1-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C5:EE_|CH3PR12MB9028:EE_ X-MS-Office365-Filtering-Correlation-Id: f779190a-bdc8-44d2-7b48-08de2218dbf7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 18:25:29.7380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f779190a-bdc8-44d2-7b48-08de2218dbf7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9028 This series introduces support for AMD IOMMU nested page table translation with the host (v1) and guest (v2) page tables. In this mode, the AMD IOMMU driver configures the Device Table Entry (DTE) with host page table root pointer, which is configured by allocating domain with page table type IOMMU_HWPT_ALLOC_NEST_PARENT. The guest page tables and Guest CR3 (GCR3) tables are managed by Guest OS, and stored in the guest DTE (gDTE) in guest memory. VMM is responsible for passing gDTE information to the host IOMMU driver using struct iommu_hwpt_amd_guest when allocating a domain type IOMMU_DOMAIN_NESTED. Then, the gDTE is parsed and program onto host DTE by the AMD IOMMU driver. In addition, this series introduces base code for IOMMUFD vIOMMU for AMD IOMMU, and implements vIOMMU-based nested domain allocation interface. The struct nested_domain to store nested domain information, and set_dte_nested() helper function to handle DTE programing for the nested domain. The series is separated into two parts: * Patch 1-5 are preparatory patches. * Patch 6-17 implement nest-parent and nested domains support for IOMMUFD vIOMMU. Note: This series is rebased on top of: * Git repo: git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git Branch: next Commit: 91920a9d87f5 ("Merge branches 'arm/smmu/updates', 'arm/smmu/bindings', 'mediatek', 'nvidia/tegra', 'amd/amd-vi' and 'core' into next") * [PATCH v5] iommu/amd: Add support for hw_info for iommu capability query https://lore.kernel.org/linux-iommu/20250926141901.511313-1-suravee.suthikulpanit@amd.com/T/#u Changes from V4: (https://lore.kernel.org/linux-iommu/20251009235755.4497-1-suravee.suthikulpanit@amd.com) * Remove unused patch to modify device_flush_dte(). * Remove unused patch to modify iommu_completion_wait() * Remove unused patch to modify update_dte256() * Patch 5: (new) * Patch 11: - Move gdomid_array from protection_domain to struct amd_iommu_viommu. - Introduce struct guest_domain_mapping_info. - Rework logic to support multiple viommu. - Introduce amd_iommufd_viommu_destroy() to clean up data structurs * Patch 13: - Rework based on Jason's suggestion - Rebase on top of gen_pt changes, which affect the logic in set_dte_entry() * Patch 14 - Modify to use the new amd_iommu_update_dte() per Jason's suggestion. Thanks, Suravee Suravee Suthikulpanit (14): iommu/amd: Rename DEV_DOMID_MASK to DTE_DOMID_MASK iommu/amd: Make amd_iommu_pdom_id_alloc() non-static iommu/amd: Make amd_iommu_pdom_id_free() non-static iommu/amd: Make amd_iommu_make_clear_dte() non-static inline iommu/amd: Introduce helper function amd_iommu_update_dte() iommufd: Introduce data struct for AMD nested domain allocation iommu/amd: Always enable GCR3TRPMode when supported. iommu/amd: Add support for nest parent domain allocation iommu/amd: Introduce struct amd_iommu_viommu iommu/amd: Add support for nested domain allocation iommu/amd: Introduce gDomID-to-hDomID Mapping and handle parent domain invalidation iommu/amd: Refactor persistent DTE bits programming into amd_iommu_make_clear_dte() iommu/amd: Refactor logic to program the host page table in DTE iommu/amd: Add support for nested domain attach/detach drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu.h | 36 ++++ drivers/iommu/amd/amd_iommu_types.h | 48 +++++- drivers/iommu/amd/init.c | 8 + drivers/iommu/amd/iommu.c | 221 +++++++++++++++--------- drivers/iommu/amd/iommufd.c | 50 ++++++ drivers/iommu/amd/iommufd.h | 5 + drivers/iommu/amd/nested.c | 259 ++++++++++++++++++++++++++++ include/uapi/linux/iommufd.h | 11 ++ 9 files changed, 558 insertions(+), 82 deletions(-) create mode 100644 drivers/iommu/amd/nested.c -- 2.34.1