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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59580405693sm3023727e87.76.2025.11.17.01.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Nov 2025 01:05:42 -0800 (PST) From: Marcus Folkesson Date: Mon, 17 Nov 2025 10:05:02 +0100 Subject: [PATCH RESEND v3 5/5] docs: i2c: i2c-topology: add section about bus speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251117-i2c-mux-v3-5-696c83e3505a@gmail.com> References: <20251117-i2c-mux-v3-0-696c83e3505a@gmail.com> In-Reply-To: <20251117-i2c-mux-v3-0-696c83e3505a@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8159; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=Pi8rg8aDh1DzKC60rhi2IjK0Atc4BXPx6hzEn3Z2p8o=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpGuVYDNc2zbHJruLUp5iqBcRmx68oP2FwF21ZE olHkhj6ysaJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaRrlWAAKCRCIgE5vWV1S MnsMD/0dDrtOrZWY7f8n04gRG4qqZeolpcQCyrxdYCd88B8QfjW9T/eFOOEXL0dfOqGs6aTOZT4 jEda0NvWG7OrdEvfHINxqTlEF8qAhrSrIInMMIphrfF45xdJYYXeaT11R7U4AXjvpuM2glCETAU FalnstcWYv2UypkNkJwqaQyB4Vu4PRbD+UiJAKDW+wkWnM26PJ8D0yDLzq58c00RSm2R7ARVWp4 Nwr0wzUlw2x//y0JzCjF52yI5o6iPiAPMaa7XATtmZz5jR9mJaUQ2hZNtIWXZ2ZCtTjlFVfZEfB 8HnnNi9qcZQm/usFqpgqgPywZyv6ClTFdiIW7FJJN6AdrpCOCm0kd5XfP9EC2Lkl2SGuAE0xfFo ThOizwU/S2lyQAPwSbdGFe2jrFohMUGwYf7lm08+jcc6wss4bRftPo1z5QbQAZoj0XEvIgTuTzo eb8UzVvIvJnPKWbo/1fTBF9VRSKMmWXHGsebm7Bm9WlED0Mfr5kVpRkDxKrL0twE33laabWsd/o O9ndpIq0JaxThshPaks6j5GixcvwmCJ6k/pfgKGCmqbiqlhrqbu1F5L8LA/lPQrqoZIZrw82irR /CkFgCmM3HN2CjGISZxTf5vn+uHSnlzxl42YGECS50F3tfywiZ68gXtsE/NaXcER3ybXx+mVaAV GvVa6kF1eJabsew== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Describe what needs to be consideraed and taken into account when using different bus speeds for different mux channels. Signed-off-by: Marcus Folkesson --- Documentation/i2c/i2c-topology.rst | 176 +++++++++++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+) diff --git a/Documentation/i2c/i2c-topology.rst b/Documentation/i2c/i2c-topology.rst index 48fce0f7491b..2c4a1364ce82 100644 --- a/Documentation/i2c/i2c-topology.rst +++ b/Documentation/i2c/i2c-topology.rst @@ -367,6 +367,182 @@ When D1 or D2 are accessed, accesses to D3 and D4 are locked out while accesses to D5 may interleave. When D3 or D4 are accessed, accesses to all other devices are locked out. +Bus Speed and I2C Multiplexers +================================ + +I2C bus multiplexers allows multiple downstream channels to be exposed +as separate I2C adapters which also could set their own bus speed. + +The multiplexer itself cannot change the bus speed as it use the upstream +clock and data lines to communicate with the downstream devices. The speed +is therfor changed in the root adapter resulting in that the whole bus is +affected. + +This increases the complexity of the topology and some considerations must +be taken into. + +Bus speed +---------- + +Downstream channels of an I2C multiplexer can only operate at the same or +lower bus speed as the upstream bus. This is because the upstream bus may +have devices that cannot operate at higher speeds and those will be affected +by the speed change. + +The example below illustrates the problem. +The root adapter is operating at 100kHz. D2 can only operate with 100kHz, +but D2 can operate at 400kHz. When D1 is selected, the bus speed of the +root adapter would have to be is set to 400kHz, a speed that D2 may not support. + +This topology is therefor not allowed: :: + + .----------. 400kHz .--------. + .--------. 100kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 | + | '----------' + | .--------. + '--| dev D2 | + '--------' + + +This topology is allowed: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' + +Preferred topology +------------------- + +The preferred topology when using different bus speeds is to have the multiplexer +connected directly to the root adapter without any devices as siblings. +By this arrangement, the bus speed can be changed without affecting any other devices +and many of the caveats are avoided. + +Other multiplexers in parallell is still okay as those are locked out during transfers. + +This is the preferred topology: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' +Locking +-------- + +If the multiplexer is mux-locked, transfers to D3 may interleave between the +select-transfer-deselect to D1 or D2. +This results in a situation where the bus speed to D3 may be lower than it +is supposed to be. This is usually not a problem. + +This topology is allowed but some transfers to D3 may be at 100kHz: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +Multiple muxes in series +-------------------------- + +When multiple muxes are used in series the same rules applies. + +Transfers to D3 may interleave between select-transfer-deselect to D1, which +results that the bus speed to D2 or D3 will be at 100KHz. + +Transfers to D2 may interleave between select-transfer-deselect to D1, which +results in that the bus speed to D1 may be at 400kHz as the transfer to D2 +will set the bus speed to before the transfer to D1 starts. + +This is probably a bad topology :: + + .----------. 400kHz .----------. 100kHz .--------. + .--------.400kHz | mux- |--------| mux- |--------| dev D1 | + | root |--+----| locked | 400kHz | locked | '--------' + '--------' | | mux M1 |--. | mux M2 | + | '----------' | '----------' + | .--------. | .--------. + '--| dev D3 | '--| dev D2 | + '--------' '--------' + +Multiple muxes in parallell +---------------------------- + +When multiple muxes are used in parallell all access to other muxes are locked out +so this is not a problem. + +If the muxes are mux-locked, access to D3 may still interleave though. + +In the example below, D3 may not interleave between select-transfer-deselect for D1 +or D2 as both muxes are parent-locked: :: + + + .----------. 100kHz .--------. + | parent- |----------| dev D1 | + .--| locked | '--------' + | | mux M1 | + | '----------' + | .----------. 400KHz .--------. + .--------. 400kHz | parent- |---------| dev D2 | + | root |--+------| locked | '--------' + '--------' | | mux M2 | + | '----------' + | .--------. + '--| dev D3 | + '--------' + +Idle state +----------- + +Muxes have an idle state, which is the state the channels is put into when no channel +is active. The state is typically one of the following: + +- All channels are disconnected +- The last selected channel is left as-is +- A predefined channel is selected + +Muxes that support an idle state where all channels are disconnected are preferred when using +different bus speeds. Otherwise high bus speeds may "leak" through to devices that +may not support that higher speed. + +Consider the following example: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +If the idle state of M1 is: +- All channels disconnected: No problem, D1 and D2 are not affected by communication + to D3. +- Last selected channel: Problem if D1 was the last selected channel. High speed + communication to D3 will be "leaked" to D1. +- Predefined channel: Problem, if the predefined channel D1. Set predefined channel + to D2 as D2 may handle 400kHz. + +Supported controllers +----------------------- + +Not all I2C controllers support setting the bus speed dynamically. +At the time of writint, the following controllers has support: + +============================ ============================================= +i2c-davinci Supports dynamic bus speed +============================ ============================================= Mux type of existing device drivers =================================== -- 2.51.2