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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 10:25:48.5254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c434401-c832-4d2e-2533-08de25c3ad17 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE16.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6978 Add support for the Tegra410 SoC, which has 4 I2C controllers. The controllers are feature-equivalent to Tegra264; only the register offsets differ. Please note that this series is rebased on: https://lore.kernel.org/linux-tegra/20251115042632.69708-1-akhilrajeev@nvidia.com/T/#t Kartik Rajput (4): i2c: tegra: Introduce tegra_i2c_variant to identify DVC and VI i2c: tegra: Move variant to tegra_i2c_hw_feature i2c: tegra: Add logic to support different register offsets i2c: tegra: Add support for Tegra410 drivers/i2c/busses/i2c-tegra.c | 564 +++++++++++++++++++++++---------- 1 file changed, 405 insertions(+), 159 deletions(-) -- 2.43.0