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Mon, 17 Nov 2025 02:25:38 -0800 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v2 1/4] i2c: tegra: Introduce tegra_i2c_variant to identify DVC and VI Date: Mon, 17 Nov 2025 15:55:27 +0530 Message-ID: <20251117102530.903555-2-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251117102530.903555-1-kkartik@nvidia.com> References: <20251117102530.903555-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|SA1PR12MB9491:EE_ X-MS-Office365-Filtering-Correlation-Id: 89bfa3d0-8ba4-4763-6f08-08de25c3ad58 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?krLy7aAl9B6VEeH0CeKyQPyVr/rzBuKJWvBj78LO3mDZdbD0AevICMMuGdms?= =?us-ascii?Q?2cDjBke715kG/Vv93yonDW4m5MnejmQ4GL9jLsPNjjSqSjmiP7klGBNzFcjO?= =?us-ascii?Q?ZeHSP9gj8PzNCz8FdVk3i13NSWwVlnwiqretFANo03H8Q1/djaVXasdxaEFp?= =?us-ascii?Q?7UDdWTGtj/n+hUcTYt1UbdZ/E1J6G1GB22i/JgoZiYIVXQw/vnHrCMZdY03l?= =?us-ascii?Q?NcoFpZNBx83XwK4cH9AI/lMtHWZccmoRo4VNhfYAIso4CIZS0b2jHxLXiHk0?= =?us-ascii?Q?/iHGUJiICYiR7SYWuyWrcz41BWUWiBUAQPws9LxA/wnL+K1Y8kbKBZuGH+VB?= =?us-ascii?Q?gLGemGqJrLUgsXrQXtP4X0mrVx7PgHcsd1fHZrm8gXCxqmNUtpqf7BqaSusV?= =?us-ascii?Q?7xH6VGopVxvh7Rc2kY1VNwn/iedbJbzQBF0t87tyf0zFLGSl8IrA4jT9uw6P?= =?us-ascii?Q?SCaAjb4OSw0jlC+a1WbxTe8K4/NNJY8HzJfd3CV2FIhhmJ2+GzEGW4FtUozG?= =?us-ascii?Q?OigW7/H+0JNLC8MgKvcXEsQCKMgqJigtmuwX6lKt6LdwJJA9s3MDKkLjJsCQ?= =?us-ascii?Q?JJRynN6IWUp9yyNMyeTm5KTgU5RlqjHlkBqTNGwLBuDjEFuStZi7ar3zVA0g?= =?us-ascii?Q?7JjtQQxk0BPUotIcpmPprpYSh6ihoUQtE48+DAYn5kaKEdia8dubWlMpunid?= =?us-ascii?Q?GD2AUkTRjuidIlMODuXUbjjjYL0/U+tHiJoyIQzHU7EgGbh8DkXgDtTt+yXr?= =?us-ascii?Q?Je4P+0eyfmhcuAZJZ78oa+D5d6zzLpsP6mtBvpq1NEesSdDFPyx4VGtPKroU?= =?us-ascii?Q?NzVUlJ317LZm2ehlWlX2WzaKr03MdkrhE2OOe48iDjV085nnoJ0GG121MTBV?= =?us-ascii?Q?g2vjvHcMWJpKxEftJY+B4qpbAxPh+UhgQfZeC7KQda0ezosr/m1bPo2me5ox?= =?us-ascii?Q?iVWXBM+iTYWuULzOMdCjPLNKG+a/adlvKxcxdMHrLIM9MjmqzUI3dM32Uwro?= =?us-ascii?Q?DFcTlcbkLsAVBxcdC0fi7BzP/cQTXnRqOFrvvtQpDumIHABLxcURzu9PZNnH?= =?us-ascii?Q?5oLlv8o6qqnvVrt1t2onLT93GzZ45+Afw4wlKchH1oEDgPkNszEpwDBUgMrt?= =?us-ascii?Q?4n21zKbV30ajC9HO0AM/4mn+VYY1Kt1Y7avbTGJsgGGxAHhxe8nU+A230qph?= =?us-ascii?Q?u9deah2omCrg9vFd+cyexNdV+ZP1viovESq+wangRgxPtCSYMFtSxnh3YtX9?= =?us-ascii?Q?aaNRpuLRDkB1kzaEzXqRNas9XEMDyBpFUkdmPZ4gIL0/lypJWEFVyA1iN9IM?= =?us-ascii?Q?TpSv1xUFHxSMCNhOF66WBVlSktTGjBQYH8mT3O7basBffUV5pyr/NISLK3DH?= =?us-ascii?Q?jXc7zGU6T3rDIcCkd2A7gHXfQfJHufMPgjvKCW9KRUEiwl+wNDjndje4yQf0?= =?us-ascii?Q?qb3xffnX498p4fr9PiSYh2uKAroGKNHkW0763Sl0bII8Gpv9PcTx1DU41/xg?= =?us-ascii?Q?JT/iDWz2Vx9PMdhSP5ZBYE/o1EaJSdZYPqEDjGsdjEhrdsAROJZcXOiMJeUB?= =?us-ascii?Q?qGUlFvqkJpznSb1cBBsNsmAUVRLRgosGB6Mm7fuo?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 10:25:48.9136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89bfa3d0-8ba4-4763-6f08-08de25c3ad58 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9491 Replace the per-instance boolean flags with an enum tegra_i2c_variant since DVC and VI are mutually exclusive. Update IS_DVC/IS_VI and variant initialization accordingly. Suggested-by: Jon Hunter Signed-off-by: Kartik Rajput --- drivers/i2c/busses/i2c-tegra.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index c89ab76a327f..9ef78c279c67 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -171,6 +171,18 @@ enum msg_end_type { MSG_END_CONTINUE, }; +/* + * tegra_i2c_variant: Identifies the variant of I2C controller. + * @TEGRA_I2C_VARIANT_DEFAULT: Identifies the default I2C controller. + * @TEGRA_I2C_VARIANT_DVC: Identifies the DVC I2C controller, has a different register layout. + * @TEGRA_I2C_VARIANT_VI: Identifies the VI I2C controller, has a different register layout. + */ +enum tegra_i2c_variant { + TEGRA_I2C_VARIANT_DEFAULT, + TEGRA_I2C_VARIANT_DVC, + TEGRA_I2C_VARIANT_VI, +}; + /** * struct tegra_i2c_hw_feature : per hardware generation features * @has_continue_xfer_support: continue-transfer supported @@ -269,8 +281,7 @@ struct tegra_i2c_hw_feature { * @base_phys: physical base address of the I2C controller * @cont_id: I2C controller ID, used for packet header * @irq: IRQ number of transfer complete interrupt - * @is_dvc: identifies the DVC I2C controller, has a different register layout - * @is_vi: identifies the VI I2C controller, has a different register layout + * @variant: This represents the I2C controller variant. * @msg_complete: transfer completion notifier * @msg_buf_remaining: size of unsent data in the message buffer * @msg_len: length of message in current transfer @@ -323,12 +334,13 @@ struct tegra_i2c_dev { bool atomic_mode; bool dma_mode; bool msg_read; - bool is_dvc; - bool is_vi; + enum tegra_i2c_variant variant; }; -#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc) -#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi) +#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \ + (dev)->variant == TEGRA_I2C_VARIANT_DVC) +#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \ + (dev)->variant == TEGRA_I2C_VARIANT_VI) static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) @@ -1914,13 +1926,15 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); i2c_dev->multimaster_mode = multi_mode; + i2c_dev->variant = TEGRA_I2C_VARIANT_DEFAULT; + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) - i2c_dev->is_dvc = true; + i2c_dev->variant = TEGRA_I2C_VARIANT_DVC; if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) - i2c_dev->is_vi = true; + i2c_dev->variant = TEGRA_I2C_VARIANT_VI; } static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) -- 2.43.0