From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 243C0363C70 for ; Wed, 19 Nov 2025 17:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763573214; cv=none; b=Gi452JXQGIXbzZUGXyHmgtQdn+asFopt4HDmHK4l+lhSgsoAQY0Epi++FRudSbao5Iq7kMgvkTgwfPAoRoCJ+Tkkn2TscgIPd+k4VkwJjzVG5hR4cvVuHRN2yJ7BHSafZCYuUGgZbfLbUEtmJcJqRf3U4b5+wsvK0Cq0dOUMx0I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763573214; c=relaxed/simple; bh=iKykSqw/ow3MeQH/fXCJEn5pg5dV71TDR8QZs3QgAXw=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=PeGrys41QRVDiipa4R7qdWwUFCVf7u969KFg2BwRBrK8QrQJglDttSDk6uQBtcDc2wqXUPSRhkfISFXcA5mpJ+94MpIwTo7FSOVbdhcIRM2O01yjiYRbwRQzNtHqcFmajKpneGuzRffNecKDoq6pb4g2/HWoIGJqHqqFeeBUEYA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VtTNsNFR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=8U27NzRd; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VtTNsNFR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="8U27NzRd" Message-ID: <20251119172549.194111661@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1763573210; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LBXt21+CfCncuqpBRLSzREJZFAKCZZ+2A7+Hi1SzXXU=; b=VtTNsNFR7+mLDeK60nDHVzOtwbTu0hhcV3+zREENxGobPbQpiUvbusmM+4T66F455gLcsJ KN9ywmIzCAAoFUlOoBukFtiipmbjzDbUOJ7vu3JiTOr8EDexwOEt75UO6Mkgd/S3rqSmaO ONoXUgsVgE4iAdFDGadRM2lf3MbVE2lAXLMHLmpl0mOb970SG+r7KVVg3SpOCEpEIQpvjD 06VSn4/V2kmsmHPhjhSkHqtsx09pgrm95yX9u0iRkd5aEwai4RkMO/RF4c6q7t4Ji0T+Ga its9OdJRQ4D1zEME900R/iJj3StsMzFJy4zHG0psxREQuv5HZPRskAWQgsVBEg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1763573210; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LBXt21+CfCncuqpBRLSzREJZFAKCZZ+2A7+Hi1SzXXU=; b=8U27NzRdslTdSvbABIRbeXPNPK9zEh6Y4enfpnvbECyXP7kH2GOzO7mpREXCMEdWR4Rv4E 5TilXIHcWJxVyMCw== From: Thomas Gleixner To: LKML Cc: Peter Zijlstra , Gabriele Monaco , Mathieu Desnoyers , Michael Jeanson , Jens Axboe , "Paul E. McKenney" , "Gautham R. Shenoy" , Florian Weimer , Tim Chen , Yury Norov , Shrikanth Hegde Subject: [patch V5 03/20] sched/mmcid: Cacheline align MM CID storage References: <20251119171016.815482037@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Date: Wed, 19 Nov 2025 18:26:49 +0100 (CET) Both the per CPU storage and the data in mm_struct are heavily used in context switch. As they can end up next to other frequently modified data, they are subject to false sharing. Make them cache line aligned. Signed-off-by: Thomas Gleixner Reviewed-by: Mathieu Desnoyers --- include/linux/rseq_types.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/include/linux/rseq_types.h +++ b/include/linux/rseq_types.h @@ -112,7 +112,7 @@ struct sched_mm_cid { */ struct mm_cid_pcpu { unsigned int cid; -}; +}____cacheline_aligned_in_smp; /** * struct mm_mm_cid - Storage for per MM CID data @@ -126,7 +126,7 @@ struct mm_mm_cid { struct mm_cid_pcpu __percpu *pcpu; unsigned int nr_cpus_allowed; raw_spinlock_t lock; -}; +}____cacheline_aligned_in_smp; #else /* CONFIG_SCHED_MM_CID */ struct mm_mm_cid { }; struct sched_mm_cid { };