From: Zhao Liu <zhao1.liu@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H . Peter Anvin" <hpa@zytor.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Chao Gao <chao.gao@intel.com>, Zhao Liu <zhao1.liu@intel.com>,
Xudong Hao <xudong.hao@intel.com>
Subject: [PATCH 4/4] KVM: x86: Advertise AVX10_VNNI_INT CPUID to userspace
Date: Thu, 20 Nov 2025 13:07:20 +0800 [thread overview]
Message-ID: <20251120050720.931449-5-zhao1.liu@intel.com> (raw)
In-Reply-To: <20251120050720.931449-1-zhao1.liu@intel.com>
Define and pass AVX10_VNNI_INT CPUID through to the guest.
AVX10_VNNI_INT (0x24.0x1.ECX[bit 2]) is a discrete feature bit
introduced on Intel Diamond Rapids, which enumerates the support for
EVEX VPDP* instructions for INT8/INT16 [*].
Since this feature has no actual kernel usages, define it as a KVM-only
feature in reverse_cpuid.h.
Advertise new CPUID subleaf 0x24.0x1 with AVX10_VNNI_INT bit to
userspace for guest use. It's safe since no additional enabling work
is needed in the host kernel.
[*]: Intel Advanced Vector Extensions 10.2 Architecture Specification
(rev 5.0).
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721
---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/cpuid.c | 18 +++++++++++++++++-
arch/x86/kvm/reverse_cpuid.h | 4 ++++
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index db7bf364f4fc..992a0abbcc48 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -777,6 +777,7 @@ enum kvm_only_cpuid_leafs {
CPUID_8000_0021_ECX,
CPUID_7_1_ECX,
CPUID_1E_1_EAX,
+ CPUID_24_1_ECX,
NR_KVM_CPU_CAPS,
NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS,
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 984fbee2795e..58db5a87757e 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1074,6 +1074,10 @@ void kvm_set_cpu_caps(void)
F(AVX10_512),
);
+ kvm_cpu_cap_init(CPUID_24_1_ECX,
+ F(AVX10_VNNI_INT),
+ );
+
kvm_cpu_cap_init(CPUID_8000_0001_ECX,
F(LAHF_LM),
F(CMP_LEGACY),
@@ -1650,6 +1654,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
break;
}
+ max_idx = entry->eax = min(entry->eax, 1u);
/*
* The AVX10 version is encoded in EBX[7:0]. Note, the version
* is guaranteed to be >=1 if AVX10 is supported. Note #2, the
@@ -1659,9 +1664,20 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
cpuid_entry_override(entry, CPUID_24_0_EBX);
entry->ebx |= avx10_version;
- entry->eax = 0;
entry->ecx = 0;
entry->edx = 0;
+
+ /* KVM only supports up to 0x24.0x1, capped above via min(). */
+ if (max_idx >= 1) {
+ entry = do_host_cpuid(array, function, 1);
+ if (!entry)
+ goto out;
+
+ cpuid_entry_override(entry, CPUID_24_1_ECX);
+ entry->eax = 0;
+ entry->ebx = 0;
+ entry->edx = 0;
+ }
break;
}
case KVM_CPUID_SIGNATURE: {
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index 99ec9e656655..a240abaaa5e0 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -59,6 +59,9 @@
#define X86_FEATURE_AVX10_256 KVM_X86_FEATURE(CPUID_24_0_EBX, 17)
#define X86_FEATURE_AVX10_512 KVM_X86_FEATURE(CPUID_24_0_EBX, 18)
+/* Intel-defined sub-features, CPUID level 0x00000024:1 (ECX) */
+#define X86_FEATURE_AVX10_VNNI_INT KVM_X86_FEATURE(CPUID_24_1_ECX, 2)
+
/* CPUID level 0x80000007 (EDX). */
#define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8)
@@ -102,6 +105,7 @@ static const struct cpuid_reg reverse_cpuid[] = {
[CPUID_8000_0021_ECX] = {0x80000021, 0, CPUID_ECX},
[CPUID_7_1_ECX] = { 7, 1, CPUID_ECX},
[CPUID_1E_1_EAX] = { 0x1e, 1, CPUID_EAX},
+ [CPUID_24_1_ECX] = { 0x24, 1, CPUID_ECX},
};
/*
--
2.34.1
next prev parent reply other threads:[~2025-11-20 4:46 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 5:07 [PATCH 0/4] KVM: x86: Advertise new instruction CPUIDs for Intel Diamond Rapids Zhao Liu
2025-11-20 5:07 ` [PATCH 1/4] KVM: x86: Advertise MOVRS CPUID to userspace Zhao Liu
2026-01-23 18:03 ` Sean Christopherson
2025-11-20 5:07 ` [PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 " Zhao Liu
2026-01-23 6:02 ` Xiaoyao Li
2026-01-23 17:53 ` Sean Christopherson
2026-01-23 17:55 ` Sean Christopherson
2026-01-25 7:51 ` Zhao Liu
2026-07-15 23:08 ` Jim Mattson
2026-01-23 18:06 ` Sean Christopherson
2026-01-25 7:54 ` Zhao Liu
2025-11-20 5:07 ` [PATCH 3/4] KVM: x86: Advertise AVX10.2 CPUID " Zhao Liu
2025-11-20 5:07 ` Zhao Liu [this message]
2025-12-18 17:54 ` [PATCH 0/4] KVM: x86: Advertise new instruction CPUIDs for Intel Diamond Rapids Paolo Bonzini
2026-01-21 1:40 ` Zhao Liu
2026-01-23 6:03 ` Xiaoyao Li
2026-02-04 0:10 ` Sean Christopherson
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