From: Yao Zi <ziyao@disroot.org>
To: Drew Fustini <fustini@kernel.org>, Guo Ren <guoren@kernel.org>,
Fu Wei <wefu@redhat.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Icenowy Zheng <uwu@icenowy.me>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Han Gao <rabenda.cn@gmail.com>, Han Gao <gaohan@iscas.ac.cn>,
Yao Zi <ziyao@disroot.org>
Subject: [PATCH 1/7] dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock
Date: Thu, 20 Nov 2025 13:14:10 +0000 [thread overview]
Message-ID: <20251120131416.26236-2-ziyao@disroot.org> (raw)
In-Reply-To: <20251120131416.26236-1-ziyao@disroot.org>
Add binding ID for C910 bus clock, which takes CLK_C910 as parent and is
essential for C910 cluster's operation.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
include/dt-bindings/clock/thead,th1520-clk-ap.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h
index 09a9aa7b3ab1..68b35cc61204 100644
--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h
+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h
@@ -93,6 +93,7 @@
#define CLK_SRAM3 83
#define CLK_PLL_GMAC_100M 84
#define CLK_UART_SCLK 85
+#define CLK_C910_BUS 86
/* VO clocks */
#define CLK_AXI4_VO_ACLK 0
--
2.51.2
next prev parent reply other threads:[~2025-11-20 13:14 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 13:14 [PATCH 0/7] Implement CPU frequency scaling for TH1520 Yao Zi
2025-11-20 13:14 ` Yao Zi [this message]
2025-11-20 18:01 ` [PATCH 1/7] dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock Conor Dooley
2025-11-20 13:14 ` [PATCH 2/7] clk: thead: th1520-ap: Poll for PLL lock and wait for stability Yao Zi
2025-11-24 22:08 ` Drew Fustini
2025-11-25 3:19 ` Yao Zi
2025-11-26 14:39 ` Drew Fustini
2025-11-26 14:52 ` Drew Fustini
2025-11-26 15:16 ` Yao Zi
2025-11-20 13:14 ` [PATCH 3/7] clk: thead: th1520-ap: Add C910 bus clock Yao Zi
2025-11-26 15:46 ` Drew Fustini
2025-11-20 13:14 ` [PATCH 4/7] clk: thead: th1520-ap: Support setting PLL rates Yao Zi
2025-11-26 15:46 ` Drew Fustini
2025-11-20 13:14 ` [PATCH 5/7] clk: thead: th1520-ap: Add macro to define multiplexers with flags Yao Zi
2025-11-24 22:14 ` Drew Fustini
2025-11-25 3:25 ` Yao Zi
2025-11-26 15:47 ` Drew Fustini
2025-11-20 13:14 ` [PATCH 6/7] clk: thead: th1520-ap: Support CPU frequency scaling Yao Zi
2025-11-27 20:33 ` Drew Fustini
2025-11-20 13:14 ` [PATCH 7/7] [Not For Upstream] riscv: dts: thead: Add CPU clock and OPP table for TH1520 Yao Zi
2025-12-19 19:32 ` [PATCH 0/7] Implement CPU frequency scaling " Drew Fustini
2026-01-15 1:50 ` Drew Fustini
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