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Fri, 21 Nov 2025 13:52:46 -0800 (PST) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bd75def6314sm6399270a12.7.2025.11.21.13.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Nov 2025 13:52:45 -0800 (PST) From: Akhil P Oommen Subject: [PATCH v3 0/6] Support for Adreno 612 GPU - Respin Date: Sat, 22 Nov 2025 03:22:14 +0530 Message-Id: <20251122-qcs615-spin-2-v3-0-9f4d4c87f51d@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAA7fIGkC/23OTQqDMBAF4KtI1o0kqf+r3qN0kehYA9VoRsUi3 r0xFgptNxNe4H0zK0GwGpAUwUoszBq16Vw4nwJSNrK7A9WVy0QwEXPGYzqUmLgHe91RQaGKYsU qUHmeEdfpLdR68d71dmQLw+TY8fgkSiLQ0rStHougg2WknuaCk73QaByNffp7Zu4b79Xp1+qZU 0aZkjKK6ozlLL4YxHCY5GPXQzc8OIsPwtkPIhwiRZWWUa3qBJI/yLZtL4ud2UQnAQAA X-Change-ID: 20251015-qcs615-spin-2-ed45b0deb998 To: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Jessica Zhang Cc: Dan Carpenter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Akhil P Oommen , Jie Zhang , Qingqing Zhou , Jie Zhang , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763761959; l=3668; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=q1YoWf3ORQcN4tOPmLohOft5QpHgD41Hzvz1QG0Fgqc=; b=n7GJeHf+8hii2Tyoce/nTIdSA3kkKOm/VH7B/k6lEYSoWYKYh8aqeS2EWDWgLs5f+qvh7lPxJ obSQmr9izipCbpc6Q5wkU11+P8WrTEW6S3/oriQGLtnDgPCZG+NF+Nw X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-ORIG-GUID: S09KUAeyApt4P1DU1_SdAyDVVazOkQNt X-Authority-Analysis: v=2.4 cv=R+UO2NRX c=1 sm=1 tr=0 ts=6920df2f cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=vemyJuc05ARF21wryp8A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: S09KUAeyApt4P1DU1_SdAyDVVazOkQNt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIxMDE2NyBTYWx0ZWRfXx1Y4uoAeKkzW ILcXG+FiTyk337wcJPPbEZCMWtI1txo6EI+4AhHV3yTsTtuwzSyP9kSKTph4DLMjcQOiuhFqAOQ Ko0TOWfpFZ1WQbQ1C+wPATp4Qll3sa2AknBOwAuHwvh8hQQWEIeGZKPswBGtkZLCxmHrF98ULhc sGJS2BpogIuNOjia9AFeBJjlTf3bqoWKatzWRZwcdpoRpLqk8p+mFWa3/EnXUIKwUyOSJfj0UUc X9ONKH5xfPlDsGtIstkkYD+YdjKDo4zixxFbL9nP0lEYeTe4uLLQQeybWMGWzjME6DJR4mstLX7 ghHzQ6WPwvRAg84i2U3clfcdMLVNPykOFdl5ZfYX8xQ0EZ0Zmh0xOeuncHieLQsiEennttjGaeG R+N3ig9uUNl7TKpk2PaGO8IELRtKcQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-21_06,2025-11-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511210167 This is a respin of an old series [1] that aimed to add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. In this version, we have consolidated the previously separate series for DT and driver support, along with some significant rework. Regarding A612 GPU, it falls under ADRENO_6XX_GEN1 family and is a cut down version of A615 GPU. A612 has a new IP called Reduced Graphics Management Unit or RGMU, a small state machine which helps to toggle GX GDSC (connected to CX rail) to implement the IFPC feature. Unlike a full-fledged GMU, the RGMU does not support features such as clock control, resource voting via RPMh, HFI etc. Therefore, we require linux clock driver support similar to gmu-wrapper implementations to control gpu core clock and GX GDSC. In this series, the description of RGMU hardware in devicetree is more complete than in previous version. However, the RGMU core is not initialized from the driver as there is currently no need for it. We do perform a dummy load of RGMU firmware (now available in linux-firmware) to ensure that enabling RGMU core in the future won't break backward compatibility for users. Due to significant changes compared to the old series, all R-b tags have been dropped. Please review with fresh eyes. Last 3 patches are for Bjorn and the rest are for Rob Clark for pick up. [1] Driver: https://lore.kernel.org/lkml/20241213-a612-gpu-support-v3-1-0e9b25570a69@quicinc.com/ Devicetree: https://lore.kernel.org/lkml/fu4rayftf3i4arf6l6bzqyzsctomglhpiniljkeuj74ftvzlpo@vklca2giwjlw/ Signed-off-by: Akhil P Oommen --- Changes in v3: - Rebased on top of next-20251121 tag - Drop a612 driver support patch as it got picked up - Rename rgmu.yaml -> qcom,adreno-rgmu.yaml (Krzysztof) - Remove reg-names property for rgmu node (Krzysztof) - Use 'gmu' instead of 'rgmu' as node name (Krzysztof) - Describe cx_mem and cx_dgc register ranges (Krzysztof) - A new patch to retrieve gmu core reg resource by id - Link to v2: https://lore.kernel.org/r/20251107-qcs615-spin-2-v2-0-a2d7c4fbf6e6@oss.qualcomm.com Changes in v2: - Rebased on next-20251105 - Fix hwcg configuration (Dan) - Reuse a few gmu-wrapper routines (Konrad) - Split out rgmu dt schema (Krzysztof/Dmitry) - Fixes for GPU dt binding doc (Krzysztof) - Removed VDD_CX from rgmu dt node. Will post a separate series to address the gpucc changes (Konrad) - Fix the reg range size for adreno smmu node and reorder the properties (Konrad) - Link to v1: https://lore.kernel.org/r/20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com --- Akhil P Oommen (2): drm/msm/a6xx: Retrieve gmu core range by index dt-bindings: display/msm: gpu: Document A612 GPU Jie Zhang (3): dt-bindings: display/msm/rgmu: Document A612 RGMU arm64: dts: qcom: sm6150: Add gpu and rgmu nodes arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Qingqing Zhou (1): arm64: dts: qcom: sm6150: add the GPU SMMU node .../devicetree/bindings/display/msm/gpu.yaml | 24 +++- .../bindings/display/msm/qcom,adreno-rgmu.yaml | 126 ++++++++++++++++++ MAINTAINERS | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++ arch/arm64/boot/dts/qcom/talos.dtsi | 141 +++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 +- 6 files changed, 304 insertions(+), 10 deletions(-) --- base-commit: e93f8002e4d244f0642224635f457bc8b135c98b change-id: 20251015-qcs615-spin-2-ed45b0deb998 Best regards, -- Akhil P Oommen