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From: Nathan Chancellor <nathan@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Gabriele Monaco <gmonaco@redhat.com>,
	Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
	Michael Jeanson <mjeanson@efficios.com>,
	Jens Axboe <axboe@kernel.dk>,
	"Paul E. McKenney" <paulmck@kernel.org>,
	"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
	Florian Weimer <fweimer@redhat.com>,
	Tim Chen <tim.c.chen@intel.com>,
	Yury Norov <yury.norov@gmail.com>,
	Shrikanth Hegde <sshegde@linux.ibm.com>
Subject: Re: [patch V5 09/20] cpumask: Cache num_possible_cpus()
Date: Fri, 21 Nov 2025 17:27:55 -0700	[thread overview]
Message-ID: <20251122002755.GA2682494@ax162> (raw)
In-Reply-To: <20251119172549.578653738@linutronix.de>

Hi Thomas,

On Wed, Nov 19, 2025 at 06:27:01PM +0100, Thomas Gleixner wrote:
> Reevaluating num_possible_cpus() over and over does not make sense. That
> becomes a constant after init as cpu_possible_mask is marked ro_after_init.
> 
> Cache the value during initialization and provide that for consumption.
> 
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Reviewed-by: Yury Norov <yury.norov@gmail.com>
> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com>

After this change in -next as commit d0f23ccf6ba9 ("cpumask: Cache
num_possible_cpus()"), I am seeing boot failures on MIPS and PowerPC in
QEMU.

For MIPS using malta_defconfig:

  $ make -skj"$(nproc)" ARCH=mips CROSS_COMPILE=mips-linux- clean malta_defconfig vmlinux

  $ curl -LSs https://github.com/ClangBuiltLinux/boot-utils/releases/download/20241120-044434/mipsel-rootfs.cpio.zst | zstd -d >rootfs.cpio

  $ qemu-system-mipsel \
      -display none \
      -nodefaults \
      -cpu 24Kf \
      -machine malta \
      -kernel vmlinux \
      -initrd rootfs.cpio \
      -m 512m \
      -serial mon:stdio
  ...
  Linux version 6.18.0-rc4-00055-gd0f23ccf6ba9 (nathan@ax162) (mips-linux-gcc (GCC) 15.2.0, GNU ld (GNU Binutils) 2.45) #1 SMP Fri Nov 21 17:16:39 MST 2025
  ...
  Kernel bug detected[#1]:
  CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.18.0-rc4-00055-gd0f23ccf6ba9 #1 NONE
  Hardware name: mti,malta
  $ 0   : 00000000 00000001 00000001 00000008
  $ 4   : 00000044 82090000 00000000 00000001
  $ 8   : 00000004 808e1b98 80140000 80140000
  $12   : 00000121 00000001 00000122 82090080
  $16   : 00000000 80a17c7c 80a80000 80b10000
  $20   : 00000000 00000000 00000000 00000000
  $24   : 00000008 82095780
  $28   : 82084000 82087db0 00000000 80122358
  Hi    : 51eb5fc3
  Lo    : 28f5a1df
  epc   : 80122360 mips_smp_ipi_allocate+0x200/0x214
  ra    : 80122358 mips_smp_ipi_allocate+0x1f8/0x214
  Status: 1000a403        KERNEL EXL IE
  Cause : 00800034 (ExcCode 0d)
  PrId  : 00019300 (MIPS 24Kc)
  Modules linked in:
  Process swapper/0 (pid: 1, threadinfo=(ptrval), task=(ptrval), tls=00000000)
  Stack : 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
          00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
          00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
          00000000 9cc98073 80abb628 80a80000 00000000 80b10000 00000000 80abb650
          8200e500 80abb628 80a80000 00000000 80b10000 80110144 8200e500 808f5ae0
          ...
  Call Trace:
  [<80122360>] mips_smp_ipi_allocate+0x200/0x214
  [<80abb650>] _gp+0x10/0x50
  [<80110144>] do_one_initcall+0x64/0x2d0
  [<80ab4fc8>] kernel_init_freeable+0x100/0x2f0
  [<808e3980>] kernel_init+0x24/0x118
  [<80112258>] ret_from_kernel_thread+0x14/0x1c

  Code: 9044ac0c  2c420002  38420001 <00020336> 1000ffd1  00000000  0c238c2c  00000000  27bdff80

  ---[ end trace 0000000000000000 ]---
  ...

For PowerPC using Debian's configuration:

  $ curl -LSs https://github.com/nathanchance/llvm-kernel-testing/raw/61ffff42ede84576a9f8721d06765d8de36a912f/configs/debian/powerpc64le.config >.config

  $ make -skj"$(nproc)" ARCH=powerpc CROSS_COMPILE=powerpc64-linux- olddefconfig zImage.epapr

  $ curl -LSs https://github.com/ClangBuiltLinux/boot-utils/releases/download/20241120-044434/ppc64le-rootfs.cpio.zst | zstd -d >rootfs.cpio

  $ qemu-system-ppc64 \
      -display none \
      -nodefaults \
      -device ipmi-bmc-sim,id=bmc0 \
      -device isa-ipmi-bt,bmc=bmc0,irq=10 \
      -machine powernv \
      -kernel arch/powerpc/boot/zImage.epapr \
      -initrd rootfs.cpio \
      -m 2G \
      -serial mon:stdio
  ...
  [    0.000000] Linux version 6.18.0-rc4+ (nathan@ax162) (powerpc64-linux-gcc (GCC) 15.2.0, GNU ld (GNU Binutils) 2.45) #1 SMP PREEMPT Fri Nov 21 17:05:23 MST 2025
  ...
  [    0.615917] BUG: Kernel NULL pointer dereference on read at 0x00000130
  [    0.616333] Faulting instruction address: 0xc000000000328804
  [    0.616885] Oops: Kernel access of bad area, sig: 7 [#1]
  [    0.617185] LE PAGE_SIZE=4K MMU=Radix  SMP NR_CPUS=2048 NUMA PowerNV
  [    0.617618] Modules linked in:
  [    0.618051] CPU: 0 UID: 0 PID: 23 Comm: rcu_tasks_kthre Not tainted 6.18.0-rc4+ #1 PREEMPTLAZY
  [    0.618557] Hardware name: IBM PowerNV (emulated by qemu) POWER10 0x801200 opal:v7.1-106-g785a5e307 PowerNV
  [    0.619137] NIP:  c000000000328804 LR: c00000000032a9f0 CTR: 0000000000000000
  [    0.619478] REGS: c0000000034ffb00 TRAP: 0300   Not tainted  (6.18.0-rc4+)
  [    0.619817] MSR:  9000000000009033 <SF,HV,EE,ME,IR,DR,RI,LE>  CR: 84000884  XER: 20040000
  [    0.620396] CFAR: c00000000032a9ec DAR: 0000000000000130 DSISR: 00080000 IRQMASK: 0
  [    0.620396] GPR00: c00000000032a9ac c0000000034ffda0 c000000001cb7100 c000000002764430
  [    0.620396] GPR04: c00000007f33fb90 0000000000000000 1db5beac45697d00 c00000000344aa00
  [    0.620396] GPR08: c000000003238000 0000000000000008 0000000000000001 0000000000000002
  [    0.620396] GPR12: 0000000000000000 c000000002a7d000 c000000000269438 c00000000349bc40
  [    0.620396] GPR16: 0000000000000000 0000000000000000 c00000000290ea80 0000000000000000
  [    0.620396] GPR20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
  [    0.620396] GPR24: c00000000291e460 c000000000328270 c00000000291e460 c000000001779218
  [    0.620396] GPR28: c000000002764430 0000000000000000 c00000007f33fb90 c0000000034ffdd0
  [    0.623797] NIP [c000000000328804] rcu_tasks_invoke_cbs+0x84/0x320
  [    0.624497] LR [c00000000032a9f0] rcu_tasks_one_gp+0x450/0x680
  [    0.624851] Call Trace:
  [    0.625036] [c0000000034ffda0] [c00000000290ea80] jiffies+0x0/0x80 (unreliable)
  [    0.625517] [c0000000034ffe20] [c00000000032a9ac] rcu_tasks_one_gp+0x40c/0x680
  [    0.625869] [c0000000034fff20] [c00000000032aebc] rcu_tasks_kthread+0x10c/0x140
  [    0.626294] [c0000000034fff90] [c0000000002695bc] kthread+0x18c/0x1a0
  [    0.626608] [c0000000034fffe0] [c00000000000de58] start_kernel_thread+0x14/0x18
  [    0.627031] Code: f9210030 fbe10038 f9210040 57bd083c 393d0001 7c095040 40800028 e90300c0 7d2907b4 814300d0 79291f24 7ca8482a <81250130> 7c2004ac 7c095000 418001a0
  [    0.628259] ---[ end trace 0000000000000000 ]---
  ...

At the parent change, neither of these problems exist. If there is any
other information I can provide or patches I can test, please let me
know.

Cheers,
Nathan

  parent reply	other threads:[~2025-11-22  0:28 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-19 17:26 [patch V5 00/20] sched: Rewrite MM CID management Thomas Gleixner
2025-11-19 17:26 ` [patch V5 01/20] sched/mmcid: Revert the complex " Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 02/20] sched/mmcid: Use proper data structures Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 03/20] sched/mmcid: Cacheline align MM CID storage Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 04/20] sched: Fixup whitespace damage Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 05/20] sched/mmcid: Move scheduler code out of global header Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 06/20] sched/mmcid: Prevent pointless work in mm_update_cpus_allowed() Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 07/20] cpumask: Introduce cpumask_weighted_or() Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 08/20] sched/mmcid: Use cpumask_weighted_or() Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 09/20] cpumask: Cache num_possible_cpus() Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
     [not found]   ` <CGME20251121225645eucas1p2d0165821efb61ea8732d14b62c50af52@eucas1p2.samsung.com>
2025-11-21 22:56     ` [patch V5 09/20] " Marek Szyprowski
2025-11-22 15:36       ` Thomas Gleixner
2025-11-22 16:24         ` Marek Szyprowski
2025-11-22 19:09           ` Paul E. McKenney
2025-11-23 19:03         ` [tip: core/rseq] cpu: Initialize __num_possible_cpus correctly tip-bot2 for Thomas Gleixner
2025-11-22 18:47       ` [patch V5 09/20] cpumask: Cache num_possible_cpus() Paul E. McKenney
2025-11-22 19:10         ` Thomas Gleixner
2025-11-22  0:27   ` Nathan Chancellor [this message]
2025-11-26  4:36   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 10/20] sched/mmcid: Convert mm CID mask to a bitmap Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 11/20] signal: Move MMCID exit out of sighand lock Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 12/20] sched/mmcid: Move initialization out of line Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 13/20] sched/mmcid: Provide precomputed maximal value Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 14/20] sched/mmcid: Serialize sched_mm_cid_fork()/exit() with a mutex Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 15/20] sched/mmcid: Introduce per task/CPU ownership infrastructure Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 16/20] sched/mmcid: Provide new scheduler CID mechanism Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 17/20] sched/mmcid: Provide CID ownership mode fixup functions Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 18/20] irqwork: Move data struct to a types header Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 19/20] sched/mmcid: Implement deferred mode change Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 20/20] sched/mmcid: Switch over to the new mechanism Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-22  0:43   ` [patch V5 20/20] " Nathan Chancellor
2025-11-22 15:02     ` Thomas Gleixner
2025-11-22 16:54       ` Shrikanth Hegde
2025-11-23 19:03       ` [tip: core/rseq] sched/mmcid: Ensure that per CPU threshold is > 0 tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` [tip: core/rseq] sched/mmcid: Switch over to the new mechanism tip-bot2 for Thomas Gleixner
2026-01-28  0:01 ` [patch V5 00/20] sched: Rewrite MM CID management Ihor Solodrai
2026-01-28  8:46   ` Peter Zijlstra
2026-01-28 11:57   ` Thomas Gleixner
2026-01-28 12:58     ` Shrikanth Hegde
2026-01-28 13:56       ` Thomas Gleixner
2026-01-28 22:24         ` Thomas Gleixner
2026-01-28 22:33           ` Ihor Solodrai
2026-01-28 23:08             ` Ihor Solodrai
2026-01-29 17:06               ` Thomas Gleixner

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