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Sat, 22 Nov 2025 06:13:41 -0800 From: To: , , , , , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 RESEND 7/7] vfio/nvgrace-gpu: wait for the GPU mem to be ready Date: Sat, 22 Nov 2025 14:13:41 +0000 Message-ID: <20251122141341.3644-1-ankita@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992B:EE_|SJ0PR12MB8168:EE_ X-MS-Office365-Filtering-Correlation-Id: 787fe85a-7b14-4c50-2931-08de29d15be7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?LJsl+8Y/wxUXFYCDn/RlSCl/y4tVgMY3/zKEqXZdn/dxKioqytYKzWUp74HN?= =?us-ascii?Q?DNkSiCmfqcQDgtKONuKwDE7Hds9TKOyULFEYoSpLFQTzx0ObbmTkLis14QLQ?= =?us-ascii?Q?NePfMmL/M82tyKZB79mv1sjSa3M9RcbyYXi0XEyYSIPRqJRbbhq6OZf62F+4?= =?us-ascii?Q?iZ/7s2M4H8P7f5yqrOZECiMCaGKt2IxNeQ1yhGbKzQTx5PrvUpD1B7qu8HWt?= =?us-ascii?Q?Jp7mqHQ7sBDX+KigQQvaEDzOX0zhdRHvCUXhlh+5DwfTeD08G+DXZ/Ly/uTy?= =?us-ascii?Q?e+HL3/pW/F1K8fdq/YJlIxD5tB1PJ9jE6qdQcpLNOUS+lWkqjRZ88rwEZlvL?= =?us-ascii?Q?IJN1Hn+4RF6CsPISU/VJt4ewqUh0hsJnQArCq4RzPqOLFuCU9EARIVZH8Q38?= =?us-ascii?Q?k2vFXSRQxsEyc/4+DyWSayJ4LwwY41FOHOWorD7df7+14o+t+70I33iR+zoC?= =?us-ascii?Q?KvNxklpsGdAF8COIsTVO0SsC11m9+k2tXd0GcLRWmyAMpu3kymFqFhDGe1pq?= =?us-ascii?Q?yB7wyZKch5HTF/mrAz+J8Nn2YpEu1aDnW8GbqMt+PAdanCvXgD33nPkFEf4m?= =?us-ascii?Q?W/hVDPaSg+nxp6vGf483TR22MA7DQln+UObWOgj/nkgHZy2GohUh6j7wKfWY?= =?us-ascii?Q?GKYUQjMHOBZdz94Snl1MXZAgRrJjn/9hTnpnDdZee9SzbsX9SF7SSsCr4eQn?= =?us-ascii?Q?kxHzw+Yfvjp+OV9/s11GZhh1jG3DkoSKjDwJJkMxne5gTXwUcOMB8TUE3tpD?= =?us-ascii?Q?0p0Af9eQLOMl0iwcpzMFFaOql4So8lEqxIWT0vEQ5DKX/dHjIP4S2zcs1xhQ?= =?us-ascii?Q?/EblOxXqjlpwymUFQIzbM5TZIDbAusvdFnnzX6fFfmFUZ25zHhCOOvJQoFYV?= =?us-ascii?Q?JYSKIwqfgKxPmBVglKH57xzdu7MQnhdu2ylTAizZevSUKF/Z1zuOh4Y++wIH?= =?us-ascii?Q?uDwaWxTVi2vn6y7Nwp3Ruco1lW+gWslqUMzeDhk2ZvyFxBLYLTqc9Zu7JfUc?= =?us-ascii?Q?NHs+bSENYeKWB4SMvff29Wnk6f6y0aLQXFIM0cr3Elgx5cHxKqhifxgLH6D/?= =?us-ascii?Q?Ch8ttQs+KrEp6P7qdwnZzPJr3pMtht5UeVhLqG3lql7cpzgRKdwlH+fcHfyG?= =?us-ascii?Q?BAzBUVGx+1jbU67kRgrrT11eP9NtxZ4HbHiG0KkFkHvsYigKp9LcSz/Vz/+J?= =?us-ascii?Q?OZHWdA693rH5wqhwxA0xSwIP3xq9GgvoaVnZ5jixqL+tiGagsaCILVysnfPI?= =?us-ascii?Q?q4HB17AoAUlrfpFmVaXeODKyclS24rGFrXxjV+vknWmajfEzeve3/sGa4qCv?= =?us-ascii?Q?6OxOYhEYaS4cixd3H63IMNfufY0YD8563CFUxGklGCg4MnjkkfO/kO+WNO2D?= =?us-ascii?Q?5zpu8lWbmztzButIpP/0ris3Dv71X2+vPQnApzbJALTse7pOaSzuMrKOckdA?= =?us-ascii?Q?Gc0bAJtVxkFHU//5SEmreqx8V8c1yGakSh+dBiiPpu9lQFz0ba7tWTZMOeNM?= =?us-ascii?Q?fxXwiHtAs+lmqwQ5YC4qts8t3bF53uPd4qr3jBAe61rgkZT1ZS+PFjyQiLXf?= =?us-ascii?Q?wlZgTabRVvAUgjyE1y4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2025 14:13:49.8239 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 787fe85a-7b14-4c50-2931-08de29d15be7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8168 From: Ankit Agrawal Speculative prefetches from CPU to GPU memory until the GPU is ready after reset can cause harmless corrected RAS events to be logged on Grace systems. It is thus preferred that the mapping not be re-established until the GPU is ready post reset. The GPU readiness can be checked through BAR0 registers similar to the checking at the time of device probe. It can take several seconds for the GPU to be ready. So it is desirable that the time overlaps as much of the VM startup as possible to reduce impact on the VM bootup time. The GPU readiness state is thus checked on the first fault/huge_fault request which amortizes the GPU readiness time. The first fault is checked using the gpu_mem_mapped flag. The flag is unset on every GPU reset request by the reset_done handler. cc: Alex Williamson cc: Jason Gunthorpe cc: Vikram Sethi Suggested-by: Alex Williamson Signed-off-by: Ankit Agrawal --- drivers/vfio/pci/nvgrace-gpu/main.c | 51 +++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c index 5a2799dce417..d6a9f1cc4a25 100644 --- a/drivers/vfio/pci/nvgrace-gpu/main.c +++ b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -104,6 +104,17 @@ static int nvgrace_gpu_open_device(struct vfio_device *core_vdev) mutex_init(&nvdev->remap_lock); } + /* + * GPU readiness is checked by reading the BAR0 registers. + * + * ioremap BAR0 to ensure that the BAR0 mapping is present before + * register reads on first fault before establishing any GPU + * memory mapping. + */ + ret = vfio_pci_core_setup_barmap(vdev, 0); + if (ret) + return ret; + nvdev->gpu_mem_mapped = false; vfio_pci_core_finish_enable(vdev); @@ -152,6 +163,27 @@ static int nvgrace_gpu_wait_device_ready(void __iomem *io) return ret; } +static int +nvgrace_gpu_vfio_pci_premap_check(struct nvgrace_gpu_pci_core_device *nvdev) +{ + struct vfio_pci_core_device *vdev = &nvdev->core_device; + int ret = 0; + + down_write(&vdev->memory_lock); + if (nvdev->gpu_mem_mapped) + goto premap_exit; + + ret = nvgrace_gpu_wait_device_ready(vdev->barmap[0]); + if (ret) + goto premap_exit; + + nvdev->gpu_mem_mapped = true; + +premap_exit: + up_write(&vdev->memory_lock); + return ret; +} + static vm_fault_t nvgrace_gpu_vfio_pci_huge_fault(struct vm_fault *vmf, unsigned int order) { @@ -162,6 +194,15 @@ static vm_fault_t nvgrace_gpu_vfio_pci_huge_fault(struct vm_fault *vmf, struct mem_region *memregion; unsigned long pgoff, pfn, addr; + /* + * If the GPU memory is accessed by the CPU while the GPU is + * not ready after reset, it can cause harmless corrected RAS + * events to be logged. Make sure the GPU is ready before + * establishing the mappings. + */ + if (nvgrace_gpu_vfio_pci_premap_check(nvdev)) + return ret; + memregion = nvgrace_gpu_memregion(index, nvdev); if (!memregion) return ret; @@ -485,6 +526,16 @@ nvgrace_gpu_map_device_mem(int index, struct mem_region *memregion; int ret = 0; + /* + * If the GPU memory is accessed by the CPU while the GPU is + * not ready after reset, it can cause harmless corrected RAS + * events to be logged. Make sure the GPU is ready before + * establishing the mappings. + */ + ret = nvgrace_gpu_vfio_pci_premap_check(nvdev); + if (ret) + return ret; + memregion = nvgrace_gpu_memregion(index, nvdev); if (!memregion) return -EINVAL; -- 2.34.1