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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11c93e55af3sm65742919c88.7.2025.11.23.15.27.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Nov 2025 15:27:55 -0800 (PST) From: "Rafael V. Volkmer" To: rafael.v.volkmer@gmail.com Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, ukleinek@kernel.org Subject: [PATCH v6 2/6] pwm: tiehrpwm: use GENMASK() and FIELD_PREP() for prescalers Date: Sun, 23 Nov 2025 20:27:48 -0300 Message-ID: <20251123232748.2057-1-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251123232521.2039-1-rafael.v.volkmer@gmail.com> References: <20251123232521.2039-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Replace manual handling of CLKDIV and HSPCLKDIV with GENMASK() and FIELD_PREP(). Introduce TBCTL_PRESCALE_MASK so both fields can be updated in a single ehrpwm_modify() call, and drop the now-unused TBCTL_*_SHIFT macros. This improves readability and reduces the chance of off-by-shift errors. No functional change. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index d2151065083b..1ad8577139be 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -25,7 +25,9 @@ #define TBCTL_PRDLD_SHDW FIELD_PREP(TBCTL_PRDLD_MASK, 0) #define TBCTL_PRDLD_IMDT FIELD_PREP(TBCTL_PRDLD_MASK, 1) -#define TBCTL_CLKDIV_MASK GENMASK(12, 7) +#define TBCTL_CLKDIV_MASK GENMASK(12, 10) +#define TBCTL_HSPCLKDIV_MASK GENMASK(9, 7) +#define TBCTL_PRESCALE_MASK (TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK) #define TBCTL_CTRMODE_MASK GENMASK(1, 0) #define TBCTL_CTRMODE_UP FIELD_PREP(TBCTL_CTRMODE_MASK, 0) @@ -33,9 +35,6 @@ #define TBCTL_CTRMODE_UPDOWN FIELD_PREP(TBCTL_CTRMODE_MASK, 2) #define TBCTL_CTRMODE_FREEZE FIELD_PREP(TBCTL_CTRMODE_MASK, 3) -#define TBCTL_HSPCLKDIV_SHIFT 7 -#define TBCTL_CLKDIV_SHIFT 10 - #define CLKDIV_MAX 7 #define HSPCLKDIV_MAX 7 #define TBPRD_BITS 16 @@ -169,8 +168,8 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, *prescale_div = (1 << clkdiv) * (hspclkdiv ? (hspclkdiv * 2) : 1); if (*prescale_div >= rqst_prescaler) { - *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | - (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT); + *tb_clk_div = FIELD_PREP(TBCTL_CLKDIV_MASK, clkdiv) | + FIELD_PREP(TBCTL_HSPCLKDIV_MASK, hspclkdiv); return 0; } } @@ -247,7 +246,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, pm_runtime_get_sync(pwmchip_parent(chip)); /* Update clock prescaler values */ - ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); + ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRESCALE_MASK, tb_divval); if (pwm->hwpwm == 1) { /* Channel 1 configured with compare B register */ -- 2.43.0