From: "Rafael V. Volkmer" <rafael.v.volkmer@gmail.com>
To: rafael.v.volkmer@gmail.com
Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org,
ukleinek@kernel.org
Subject: [PATCH v6 3/6] pwm: tiehrpwm: refactor AQCTL polarity macros
Date: Sun, 23 Nov 2025 20:29:47 -0300 [thread overview]
Message-ID: <20251123232947.2085-1-rafael.v.volkmer@gmail.com> (raw)
In-Reply-To: <20251123232748.2057-1-rafael.v.volkmer@gmail.com>
Refactor the AQCTL polarity macros so that the selected channel and
count direction are explicit in the name (CHA/CHB and UP/DN). Keep the
existing up-count behaviour and introduce matching down-count variants
for the CAD/CBD events.
Centralize the action values (FRCLOW/FRCHIGH/FRCTOGGLE) as generic
AQCTL_* enums and use FIELD_PREP() with the corresponding *_MASK for all
events (CAU/CBU/CAD/CBD/ZRO). This reduces duplication and makes the
AQCTL programming more self-documenting.
No functional change intended.
Signed-off-by: Rafael V. Volkmer <rafael.v.volkmer@gmail.com>
---
drivers/pwm/pwm-tiehrpwm.c | 59 +++++++++++++++++++++++++-------------
1 file changed, 39 insertions(+), 20 deletions(-)
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 1ad8577139be..9f1be35912d3 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -50,30 +50,49 @@
#define AQSFRC 0x1A
#define AQCSFRC 0x1C
+#define AQCTL_FRCLOW 1
+#define AQCTL_FRCHIGH 2
+#define AQCTL_FRCTOGGLE 3
+
+#define AQCTL_CBD_MASK GENMASK(11, 10)
+#define AQCTL_CBD_FRCLOW FIELD_PREP(AQCTL_CBD_MASK, AQCTL_FRCLOW)
+#define AQCTL_CBD_FRCHIGH FIELD_PREP(AQCTL_CBD_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CBD_FRCTOGGLE FIELD_PREP(AQCTL_CBD_MASK, AQCTL_FRCTOGGLE)
+
#define AQCTL_CBU_MASK GENMASK(9, 8)
-#define AQCTL_CBU_FRCLOW FIELD_PREP(AQCTL_CBU_MASK, 1)
-#define AQCTL_CBU_FRCHIGH FIELD_PREP(AQCTL_CBU_MASK, 2)
-#define AQCTL_CBU_FRCTOGGLE FIELD_PREP(AQCTL_CBU_MASK, 3)
+#define AQCTL_CBU_FRCLOW FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCLOW)
+#define AQCTL_CBU_FRCHIGH FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CBU_FRCTOGGLE FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCTOGGLE)
+
+#define AQCTL_CAD_MASK GENMASK(7, 6)
+#define AQCTL_CAD_FRCLOW FIELD_PREP(AQCTL_CAD_MASK, AQCTL_FRCLOW)
+#define AQCTL_CAD_FRCHIGH FIELD_PREP(AQCTL_CAD_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CAD_FRCTOGGLE FIELD_PREP(AQCTL_CAD_MASK, AQCTL_FRCTOGGLE)
#define AQCTL_CAU_MASK GENMASK(5, 4)
-#define AQCTL_CAU_FRCLOW FIELD_PREP(AQCTL_CAU_MASK, 1)
-#define AQCTL_CAU_FRCHIGH FIELD_PREP(AQCTL_CAU_MASK, 2)
-#define AQCTL_CAU_FRCTOGGLE FIELD_PREP(AQCTL_CAU_MASK, 3)
+#define AQCTL_CAU_FRCLOW FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCLOW)
+#define AQCTL_CAU_FRCHIGH FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CAU_FRCTOGGLE FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCTOGGLE)
#define AQCTL_PRD_MASK GENMASK(3, 2)
-#define AQCTL_PRD_FRCLOW FIELD_PREP(AQCTL_PRD_MASK, 1)
-#define AQCTL_PRD_FRCHIGH FIELD_PREP(AQCTL_PRD_MASK, 2)
-#define AQCTL_PRD_FRCTOGGLE FIELD_PREP(AQCTL_PRD_MASK, 3)
+#define AQCTL_PRD_FRCLOW FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCLOW)
+#define AQCTL_PRD_FRCHIGH FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCHIGH)
+#define AQCTL_PRD_FRCTOGGLE FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCTOGGLE)
#define AQCTL_ZRO_MASK GENMASK(1, 0)
-#define AQCTL_ZRO_FRCLOW FIELD_PREP(AQCTL_ZRO_MASK, 1)
-#define AQCTL_ZRO_FRCHIGH FIELD_PREP(AQCTL_ZRO_MASK, 2)
-#define AQCTL_ZRO_FRCTOGGLE FIELD_PREP(AQCTL_ZRO_MASK, 3)
+#define AQCTL_ZRO_FRCLOW FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCLOW)
+#define AQCTL_ZRO_FRCHIGH FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCHIGH)
+#define AQCTL_ZRO_FRCTOGGLE FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCTOGGLE)
+
+#define AQCTL_CHA_UP_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_ZRO_FRCHIGH)
+#define AQCTL_CHA_UP_POLINVERSE (AQCTL_CAU_FRCHIGH | AQCTL_ZRO_FRCLOW)
+#define AQCTL_CHB_UP_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_ZRO_FRCHIGH)
+#define AQCTL_CHB_UP_POLINVERSE (AQCTL_CBU_FRCHIGH | AQCTL_ZRO_FRCLOW)
-#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_ZRO_FRCHIGH)
-#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_ZRO_FRCLOW)
-#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_ZRO_FRCHIGH)
-#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_ZRO_FRCLOW)
+#define AQCTL_CHA_DN_POLNORMAL (AQCTL_CAD_FRCLOW | AQCTL_ZRO_FRCHIGH)
+#define AQCTL_CHA_DN_POLINVERSE (AQCTL_CAD_FRCHIGH | AQCTL_ZRO_FRCLOW)
+#define AQCTL_CHB_DN_POLNORMAL (AQCTL_CBD_FRCLOW | AQCTL_ZRO_FRCHIGH)
+#define AQCTL_CHB_DN_POLINVERSE (AQCTL_CBD_FRCHIGH | AQCTL_ZRO_FRCLOW)
#define AQSFRC_RLDCSF_MASK GENMASK(7, 6)
#define AQSFRC_RLDCSF_ZRO FIELD_PREP(AQSFRC_RLDCSF_MASK, 0)
@@ -256,9 +275,9 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
aqctl_mask = AQCTL_CBU_MASK;
if (polarity == PWM_POLARITY_INVERSED)
- aqctl_val = AQCTL_CHANB_POLINVERSED;
+ aqctl_val = AQCTL_CHB_UP_POLINVERSE;
else
- aqctl_val = AQCTL_CHANB_POLNORMAL;
+ aqctl_val = AQCTL_CHB_UP_POLNORMAL;
/* if duty_cycle is big, don't toggle on CBU */
if (duty_cycles > period_cycles)
@@ -272,9 +291,9 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
aqctl_mask = AQCTL_CAU_MASK;
if (polarity == PWM_POLARITY_INVERSED)
- aqctl_val = AQCTL_CHANA_POLINVERSED;
+ aqctl_val = AQCTL_CHA_UP_POLINVERSE;
else
- aqctl_val = AQCTL_CHANA_POLNORMAL;
+ aqctl_val = AQCTL_CHA_UP_POLNORMAL;
/* if duty_cycle is big, don't toggle on CAU */
if (duty_cycles > period_cycles)
--
2.43.0
next prev parent reply other threads:[~2025-11-23 23:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-23 23:20 [PATCH v6 0/6] pwm: tiehrpwm: add .get_state and tidy register handling Rafael V. Volkmer
2025-11-23 23:25 ` [PATCH v6 1/6] pwm: tiehrpwm: use GENMASK() and FIELD_PREP() for register fields Rafael V. Volkmer
2025-11-23 23:27 ` [PATCH v6 2/6] pwm: tiehrpwm: use GENMASK() and FIELD_PREP() for prescalers Rafael V. Volkmer
2025-11-23 23:29 ` Rafael V. Volkmer [this message]
2025-11-23 23:31 ` [PATCH v6 4/6] pwm: tiehrpwm: implement .get_state callback Rafael V. Volkmer
2025-11-23 23:33 ` [PATCH v6 5/6] pwm: tiehrpwm: handle already-running channels at probe Rafael V. Volkmer
2025-11-23 23:35 ` [PATCH v6 6/6] pwm: tiehrpwm: tidy period conflict check Rafael V. Volkmer
2025-11-24 16:51 ` [PATCH v6 4/6] pwm: tiehrpwm: implement .get_state callback Uwe Kleine-König
2025-11-25 3:48 ` Rafael V. Volkmer
2025-11-25 7:52 ` Uwe Kleine-König
2025-11-25 20:39 ` Rafael V. Volkmer
2025-11-26 7:48 ` Uwe Kleine-König
2025-11-24 10:36 ` [PATCH v6 1/6] pwm: tiehrpwm: use GENMASK() and FIELD_PREP() for register fields Uwe Kleine-König
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