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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29bceb450cfsm141821675ad.74.2025.12.01.22.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Dec 2025 22:43:14 -0800 (PST) From: Yingchao Deng Subject: [PATCH v6 0/2] Add Qualcomm extended CTI support Date: Tue, 02 Dec 2025 14:42:19 +0800 Message-Id: <20251202-extended_cti-v6-0-ab68bb15c4f5@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAEuKLmkC/3WMyw6CMBBFf4XM2hJoZXis/A9DTGkHmUSotkgwh H+3sndzk3OTczYI5JkCNMkGnhYO7KYIeErADHq6k2AbGWQmizyXlaB1psmSvZmZhep0VZSIsu5 LiMrTU8/rkbu2kQcOs/Ofo77g7/0TWlBkouzUuVakUKO8uBDS11s/jBvHNA60+75/AVpRW/GvA AAA To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin Cc: Tingwei Zhang , quic_yingdeng@quicinc.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jinlong Mao , Yingchao Deng , Mao Jinlong X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764657791; l=2923; i=yingchao.deng@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=hg393qa4WowvY1wSgSubo4QC9Dr0Pfdv2DwRyxTPtgw=; b=wcqDUIuOlcN48PcoSh60fElR7YS7cSyZhiM3/r0gz9KDcL13hQ9qp6k3EK9VM94mhsjTiij2b ijP3HAfbUxwChP0W3ah7NbP9SXH1thi/0mqe+v/3l/Dg7+daVew61RF X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=QWvd9DuX5YKvc7/VfWGCElGNr3HbCyig5bEb+lUUohg= X-Proofpoint-GUID: ptKY0az6On50GhPuoTNHcyAcOh7Tkrl9 X-Authority-Analysis: v=2.4 cv=H83WAuYi c=1 sm=1 tr=0 ts=692e8a84 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=qu_5hfJKU6GsaiMghqAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: ptKY0az6On50GhPuoTNHcyAcOh7Tkrl9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjAyMDA1MSBTYWx0ZWRfX33mk9mLA/DRU U8vnOhA2zE6iZZCUEMEbVBcWOt3JcSMV24uKEFmZpZomN6Ca23ToSKP7bG7RwmLhQDuR1Rio8Qx wNvNs2bHc7UD0sMZMBBA+XHJrSY0eHHLEzuaEaprQuAGiHld7Sx+d4zXyuYCZfH9EiUTrw+hlPj 5UC4DdR4Oz0I6XMh0avA3zYI7AxyBHbNveif9ibAztn3gpr6DQvp+NiniHHrKA5W6lc/SCXp3Sq /cPE+tdadDxRUQhblfTczjarkvb8L9/yGjT1sDlDoTeQFixe4wWhBUPTM7d5x2ymWkDdyvqK3E9 swEIQyCu27tka4x3x6gPNaQ5Vg6znD0rtoL7bQB7aLBjRH+ShW7l63F/hZMwhFjGYGj0AX+7fJS YVeaAcWsKNFRRGIyKTHKOb2R4qiHRQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512020051 The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. QCOM extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Changes in v6: 1. Rename regs_idx to ext_reg_sel and add information in documentation file. 2. Reset CLAIMSET to zero for qcom-cti during probe. 3. Retrieve idx value under spinlock. 4. Use yearless copyright for qcom-cti.h. Link to v5 - https://lore.kernel.org/all/20251020-extended_cti-v5-0-6f193da2d467@oss.qualcomm.com/ Changes in v5: 1. Move common part in qcom-cti.h to coresight-cti.h. 2. Convert trigger usage fields to dynamic bitmaps and arrays. 3. Fix holes in struct cti_config to save some space. 4. Revert the previous changes related to the claim tag in cti_enable/disable_hw. Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/ Changes in v4: 1. Read the DEVARCH registers to identify Qualcomm CTI. 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and coresight_cti_reg_store() functions accordingly. 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h. Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/ Changes in v3: 1. Rename is_extended_cti() to of_is_extended_cti(). 2. Add the missing 'i' when write the CTI trigger registers. 3. Convert the multi-line output in sysfs to single line. 4. Initialize offset arrays using designated initializer. Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/ Changes in V2: 1. Add enum for compatible items. 2. Move offset arrays to coresight-cti-core Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng --- Yingchao Deng (2): coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays coresight: cti: Add Qualcomm extended CTI support .../ABI/testing/sysfs-bus-coresight-devices-cti | 11 ++ drivers/hwtracing/coresight/coresight-cti-core.c | 153 ++++++++++++++--- .../hwtracing/coresight/coresight-cti-platform.c | 16 +- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 187 ++++++++++++++++----- drivers/hwtracing/coresight/coresight-cti.h | 60 ++++++- drivers/hwtracing/coresight/qcom-cti.h | 29 ++++ 6 files changed, 369 insertions(+), 87 deletions(-) --- base-commit: 7d31f578f3230f3b7b33b0930b08f9afd8429817 change-id: 20251128-extended_cti-3ba8576629f7 Best regards, -- Yingchao Deng