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From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	iommu@lists.linux.dev, Naresh Kamboju <naresh.kamboju@linaro.org>,
	Pavankumar Kondeti <quic_pkondeti@quicinc.com>,
	Xingang Wang <wangxingang5@huawei.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Robin Murphy <robin.murphy@arm.com>,
	Jason Gunthorpe <jgg@ziepe.ca>,
	Manivannan Sadhasivam <mani@kernel.org>,
	Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Subject: [PATCH v2 4/4] PCI: Extend the pci_disable_acs_sv quirk for one more IDT switch
Date: Tue, 02 Dec 2025 19:52:51 +0530	[thread overview]
Message-ID: <20251202-pci_acs-v2-4-5d2759a71489@oss.qualcomm.com> (raw)
In-Reply-To: <20251202-pci_acs-v2-0-5d2759a71489@oss.qualcomm.com>

The IDT switch with Device ID 0x8090 used in the ARM Juno R2 development
board incorrectly raises an ACS Source Validation error on Completions for
Config Read Requests, even though PCIe r6.0, sec 6.12.1.1, says that
Completions are never affected by ACS Source Validation.

This is already handled by the pci_disable_acs_sv() quirk for one of the
IDT switch 0x80b5. Hence, extend the quirk for this device too.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
 drivers/pci/quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index a5956726a49f..314aacf5a309 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5798,6 +5798,7 @@ static void pci_disable_acs_sv(struct pci_dev *dev)
 	dev->acs_broken_cap |= PCI_ACS_SV;
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IDT, 0x80b5, pci_disable_acs_sv);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IDT, 0x8090, pci_disable_acs_sv);
 
 /*
  * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between

-- 
2.48.1


  parent reply	other threads:[~2025-12-02 14:23 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20251202142307eucas1p12a15e5656bb53f48f445c3056d4e3166@eucas1p1.samsung.com>
2025-12-02 14:22 ` [PATCH v2 0/4] PCI: Fix ACS enablement for Root Ports in OF platforms Manivannan Sadhasivam
2025-12-02 14:22   ` [PATCH v2 1/4] PCI: Enable ACS only after configuring IOMMU for " Manivannan Sadhasivam
2025-12-02 14:22   ` [PATCH v2 2/4] PCI: Cache ACS capabilities Manivannan Sadhasivam
2025-12-02 14:22   ` [PATCH v2 3/4] PCI: Disable ACS SV capability for the broken IDT switches Manivannan Sadhasivam
2025-12-02 19:15     ` Jason Gunthorpe
2025-12-09 11:20       ` Manivannan Sadhasivam
2025-12-17 15:19         ` Jason Gunthorpe
2025-12-02 14:22   ` Manivannan Sadhasivam [this message]
2025-12-03  8:46   ` [PATCH v2 0/4] PCI: Fix ACS enablement for Root Ports in OF platforms Naresh Kamboju
2025-12-03 12:04   ` Marek Szyprowski
2025-12-04 13:13     ` Marek Szyprowski
2025-12-09  7:31       ` Marek Szyprowski
2025-12-09  8:28         ` Marek Szyprowski
2025-12-09 11:15           ` Manivannan Sadhasivam
2025-12-09 12:00             ` Marek Szyprowski
2025-12-09 15:04               ` Manivannan Sadhasivam
2025-12-10 17:26                 ` Marek Szyprowski
2025-12-12  4:02                   ` Manivannan Sadhasivam
2025-12-12  7:25                     ` Marek Szyprowski

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