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Wed, 03 Dec 2025 05:27:08 -0800 (PST) Received: from hu-msarkar-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7d15e6e6e06sm20287524b3a.43.2025.12.03.05.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Dec 2025 05:27:08 -0800 (PST) From: Mrinmay Sarkar Date: Wed, 03 Dec 2025 18:56:48 +0530 Subject: [PATCH 2/2] PCI: qcom-ep: Add support for firmware-managed PCIe Endpoint Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251203-firmware_managed_ep-v1-2-295977600fa5@oss.qualcomm.com> References: <20251203-firmware_managed_ep-v1-0-295977600fa5@oss.qualcomm.com> In-Reply-To: <20251203-firmware_managed_ep-v1-0-295977600fa5@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@oss.qualcomm.com, Manivannan Sadhasivam , Krishna Chaitanya Chundru , quic_vbadigan@quicinc.com, quic_shazhuss@quicinc.com, konrad.dybcio@oss.qualcomm.com, Mrinmay sarkar , Rama Krishna , Ayiluri Naga Rashmi , Nitesh Gupta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In these cases, the Linux driver should not perform resource enable or disable operations directly. Additionally, runtime PM support has been enabled to ensure proper power state transitions. This commit introduces a `firmware_managed` flag in the Endpoint configuration structure. When set, the driver skips resource handling and uses generic runtime PM calls to let firmware do resource management. A new compatible string is added for SA8255P platforms where firmware manages resources. Signed-off-by: Mrinmay Sarkar --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 80 ++++++++++++++++++++++++------- 1 file changed, 64 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index f1bc0ac81a928b928ab3f8cc7bf82558fc430474..38358c9fa7ab32fd36efcea0a42c52f1f86a523a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -168,11 +168,13 @@ enum qcom_pcie_ep_link_status { * @hdma_support: HDMA support on this SoC * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check + * @firmware_managed: Set if the Endpoint controller is firmware managed */ struct qcom_pcie_ep_cfg { bool hdma_support; bool override_no_snoop; bool disable_mhi_ram_parity_check; + bool firmware_managed; }; /** @@ -377,6 +379,15 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) { + struct device *dev = pcie_ep->pci.dev; + int ret; + + ret = pm_runtime_put_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to disable endpoint device: %d\n", ret); + return; + } + icc_set_bw(pcie_ep->icc_mem, 0, 0); phy_power_off(pcie_ep->phy); phy_exit(pcie_ep->phy); @@ -390,12 +401,22 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) u32 val, offset; int ret; - ret = qcom_pcie_enable_resources(pcie_ep); - if (ret) { - dev_err(dev, "Failed to enable resources: %d\n", ret); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable endpoint device: %d\n", ret); return ret; } + /* Enable resources if Endpoint controller is not firmware-managed */ + if (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) { + ret = qcom_pcie_enable_resources(pcie_ep); + if (ret) { + dev_err(dev, "Failed to enable resources: %d\n", ret); + pm_runtime_put_sync(dev); + return ret; + } + } + /* Perform cleanup that requires refclk */ pci_epc_deinit_notify(pci->ep.epc); dw_pcie_ep_cleanup(&pci->ep); @@ -630,16 +651,6 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, return ret; } - pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); - if (pcie_ep->num_clks < 0) { - dev_err(dev, "Failed to get clocks\n"); - return pcie_ep->num_clks; - } - - pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); - if (IS_ERR(pcie_ep->core_reset)) - return PTR_ERR(pcie_ep->core_reset); - pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); if (IS_ERR(pcie_ep->reset)) return PTR_ERR(pcie_ep->reset); @@ -652,9 +663,22 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, if (IS_ERR(pcie_ep->phy)) ret = PTR_ERR(pcie_ep->phy); - pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); - if (IS_ERR(pcie_ep->icc_mem)) - ret = PTR_ERR(pcie_ep->icc_mem); + /* Populate resources if Endpoint controller is not firmware-managed */ + if (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) { + pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); + if (pcie_ep->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return pcie_ep->num_clks; + } + + pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); + if (IS_ERR(pcie_ep->core_reset)) + return PTR_ERR(pcie_ep->core_reset); + + pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); + if (IS_ERR(pcie_ep->icc_mem)) + ret = PTR_ERR(pcie_ep->icc_mem); + } return ret; } @@ -874,6 +898,16 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie_ep); + pm_runtime_set_active(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable endpoint device: %d\n", ret); + return ret; + } + ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); if (ret) return ret; @@ -897,6 +931,12 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->debugfs = debugfs_create_dir(name, NULL); qcom_pcie_ep_init_debugfs(pcie_ep); + ret = pm_runtime_put_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to disable endpoint device: %d\n", ret); + goto err_disable_irqs; + } + return 0; err_disable_irqs: @@ -930,7 +970,15 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { .disable_mhi_ram_parity_check = true, }; +static const struct qcom_pcie_ep_cfg cfg_1_34_0_fw_managed = { + .hdma_support = true, + .override_no_snoop = true, + .disable_mhi_ram_parity_check = true, + .firmware_managed = true, +}; + static const struct of_device_id qcom_pcie_ep_match[] = { + { .compatible = "qcom,sa8255p-pcie-ep", .data = &cfg_1_34_0_fw_managed}, { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, -- 2.25.1