[PATCH 06/10] KVM/x86: Use defines for APIC related MSR emulation

[Juergen Gross <jgross@suse.com>]

Instead of "0" and "1" use the related KVM_MSR_RET_* defines in the
emulation code of APIC related MSR registers.

No change of functionality intended.

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/x86/kvm/lapic.c | 48 ++++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 0ae7f913d782..bd4c0768b270 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2339,7 +2339,7 @@ static int get_lvt_index(u32 reg)
 
 static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 {
-	int ret = 0;
+	int ret = KVM_MSR_RET_OK;
 
 	trace_kvm_apic_write(reg, val);
 
@@ -2348,7 +2348,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 		if (!apic_x2apic_mode(apic)) {
 			kvm_apic_set_xapic_id(apic, val >> 24);
 		} else {
-			ret = 1;
+			ret = KVM_MSR_RET_ERR;
 		}
 		break;
 
@@ -2365,14 +2365,14 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 		if (!apic_x2apic_mode(apic))
 			kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
 		else
-			ret = 1;
+			ret = KVM_MSR_RET_ERR;
 		break;
 
 	case APIC_DFR:
 		if (!apic_x2apic_mode(apic))
 			kvm_apic_set_dfr(apic, val | 0x0FFFFFFF);
 		else
-			ret = 1;
+			ret = KVM_MSR_RET_ERR;
 		break;
 
 	case APIC_SPIV: {
@@ -2403,7 +2403,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 		break;
 	case APIC_ICR2:
 		if (apic_x2apic_mode(apic))
-			ret = 1;
+			ret = KVM_MSR_RET_ERR;
 		else
 			kvm_lapic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 		break;
@@ -2418,7 +2418,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 	case APIC_LVTCMCI: {
 		u32 index = get_lvt_index(reg);
 		if (!kvm_lapic_lvt_supported(apic, index)) {
-			ret = 1;
+			ret = KVM_MSR_RET_ERR;
 			break;
 		}
 		if (!kvm_apic_sw_enabled(apic))
@@ -2460,7 +2460,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 	}
 	case APIC_ESR:
 		if (apic_x2apic_mode(apic) && val != 0)
-			ret = 1;
+			ret = KVM_MSR_RET_ERR;
 		break;
 
 	case APIC_SELF_IPI:
@@ -2469,12 +2469,12 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 		 * the vector, everything else is reserved.
 		 */
 		if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK))
-			ret = 1;
+			ret = KVM_MSR_RET_ERR;
 		else
 			kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0);
 		break;
 	default:
-		ret = 1;
+		ret = KVM_MSR_RET_ERR;
 		break;
 	}
 
@@ -2532,7 +2532,7 @@ EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_lapic_set_eoi);
 static int __kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data, bool fast)
 {
 	if (data & X2APIC_ICR_RESERVED_BITS)
-		return 1;
+		return KVM_MSR_RET_ERR;
 
 	/*
 	 * The BUSY bit is reserved on both Intel and AMD in x2APIC mode, but
@@ -2565,7 +2565,7 @@ static int __kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data, bool fast)
 		kvm_lapic_set_reg64(apic, APIC_ICR, data);
 	}
 	trace_kvm_apic_write(APIC_ICR, data);
-	return 0;
+	return KVM_MSR_RET_OK;
 }
 
 static int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data)
@@ -2728,23 +2728,23 @@ int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated)
 	enum lapic_mode new_mode = kvm_apic_mode(value);
 
 	if (vcpu->arch.apic_base == value)
-		return 0;
+		return KVM_MSR_RET_OK;
 
 	u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
 		(guest_cpu_cap_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 
 	if ((value & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
-		return 1;
+		return KVM_MSR_RET_ERR;
 	if (!host_initiated) {
 		if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
-			return 1;
+			return KVM_MSR_RET_ERR;
 		if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
-			return 1;
+			return KVM_MSR_RET_ERR;
 	}
 
 	__kvm_apic_set_base(vcpu, value);
 	kvm_recalculate_apic_map(vcpu->kvm);
-	return 0;
+	return KVM_MSR_RET_OK;
 }
 EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_apic_set_base);
 
@@ -3362,15 +3362,15 @@ static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data)
 
 	if (reg == APIC_ICR) {
 		*data = kvm_x2apic_icr_read(apic);
-		return 0;
+		return KVM_MSR_RET_OK;
 	}
 
 	if (kvm_lapic_reg_read(apic, reg, 4, &low))
-		return 1;
+		return KVM_MSR_RET_ERR;
 
 	*data = low;
 
-	return 0;
+	return KVM_MSR_RET_OK;
 }
 
 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data)
@@ -3385,7 +3385,7 @@ static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data)
 
 	/* Bits 63:32 are reserved in all other registers. */
 	if (data >> 32)
-		return 1;
+		return KVM_MSR_RET_ERR;
 
 	return kvm_lapic_reg_write(apic, reg, (u32)data);
 }
@@ -3396,7 +3396,7 @@ int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 	u32 reg = (msr - APIC_BASE_MSR) << 4;
 
 	if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
-		return 1;
+		return KVM_MSR_RET_ERR;
 
 	return kvm_lapic_msr_write(apic, reg, data);
 }
@@ -3407,7 +3407,7 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
 	u32 reg = (msr - APIC_BASE_MSR) << 4;
 
 	if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
-		return 1;
+		return KVM_MSR_RET_ERR;
 
 	return kvm_lapic_msr_read(apic, reg, data);
 }
@@ -3415,7 +3415,7 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
 {
 	if (!lapic_in_kernel(vcpu))
-		return 1;
+		return KVM_MSR_RET_ERR;
 
 	return kvm_lapic_msr_write(vcpu->arch.apic, reg, data);
 }
@@ -3423,7 +3423,7 @@ int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
 {
 	if (!lapic_in_kernel(vcpu))
-		return 1;
+		return KVM_MSR_RET_ERR;
 
 	return kvm_lapic_msr_read(vcpu->arch.apic, reg, data);
 }
-- 
2.51.0