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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2025 15:29:27.9118 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a84cd8d9-77d3-4b41-d540-08de366e9360 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EF.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR08MB10917 These changes address two trapping-related issues when running legacy (i.e. GICv3) guests on GICv5 hosts. The first change enables the vgic_v3_cpuif_trap static branch on GICv5 hosts with legacy support, if trapping is required. The missing enable was caught as part of debugging why UNDEFs were being injected into guests when the ICH_HCR_EL2.TC bit was set - the expected bahaviour was that KVM should handle the trapped accesses, with the guest remaining blissfully unaware. The second change fixes the specific cause of the TC bit being set in the first place. The test for the ICH_HCR_EL2_TDIR cap was checking for GICv3 CPUIF support and returning false prior to checking for GICv5 Legacy support. The result was that on GICv5 hosts, the test always returned false, and therefore the TC bit was being set. The issue is fixed by reordering the checks to check for GICv5 Legacy support first. These changes are based against kvmarm/next. Thanks, Sascha Sascha Bischoff (2): KVM: arm64: gic: Enable GICv3 CPUIF trapping on GICv5 hosts if required KVM: arm64: Correct test for ICH_HCR_EL2_TDIR cap for GICv5 hosts arch/arm64/kernel/cpufeature.c | 8 ++++---- arch/arm64/kvm/vgic/vgic-v3.c | 25 +++++++++++++++---------- arch/arm64/kvm/vgic/vgic-v5.c | 2 ++ arch/arm64/kvm/vgic/vgic.h | 1 + 4 files changed, 22 insertions(+), 14 deletions(-) -- 2.34.1=