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Wed, 17 Dec 2025 06:52:32 -0800 (PST) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47bd90f0bd9sm33323815e9.5.2025.12.17.06.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 06:52:32 -0800 (PST) Date: Wed, 17 Dec 2025 17:52:28 +0300 From: Dan Carpenter To: oe-kbuild@lists.linux.dev, Tomasz Jeznach Cc: lkp@intel.com, oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Joerg Roedel , Nick Kossifidis , Sebastien Boeuf , Lu Baolu Subject: drivers/iommu/riscv/iommu-platform.c:54 riscv_iommu_platform_probe() warn: 'iommu->irqs_count' unsigned <= 0 Message-ID: <202512141551.kZLTle5r-lkp@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 commit: 5c0ebbd3c6c6e00af112fe053e81ac0c7cafe647 iommu/riscv: Add RISC-V IOMMU platform device driver config: riscv-randconfig-r072-20251214 (https://download.01.org/0day-ci/archive/20251214/202512141551.kZLTle5r-lkp@intel.com/config) compiler: riscv64-linux-gcc (GCC) 9.5.0 If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Reported-by: Dan Carpenter | Closes: https://lore.kernel.org/r/202512141551.kZLTle5r-lkp@intel.com/ smatch warnings: drivers/iommu/riscv/iommu-platform.c:54 riscv_iommu_platform_probe() warn: 'iommu->irqs_count' unsigned <= 0 vim +54 drivers/iommu/riscv/iommu-platform.c 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 20 static int riscv_iommu_platform_probe(struct platform_device *pdev) 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 21 { 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 22 struct device *dev = &pdev->dev; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 23 struct riscv_iommu_device *iommu = NULL; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 24 struct resource *res = NULL; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 25 int vec; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 26 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 27 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 28 if (!iommu) 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 29 return -ENOMEM; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 30 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 31 iommu->dev = dev; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 32 iommu->reg = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 33 if (IS_ERR(iommu->reg)) 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 34 return dev_err_probe(dev, PTR_ERR(iommu->reg), 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 35 "could not map register region\n"); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 36 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 37 dev_set_drvdata(dev, iommu); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 38 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 39 /* Check device reported capabilities / features. */ 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 40 iommu->caps = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAPABILITIES); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 41 iommu->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 42 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 43 /* For now we only support WSI */ 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 44 switch (FIELD_GET(RISCV_IOMMU_CAPABILITIES_IGS, iommu->caps)) { 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 45 case RISCV_IOMMU_CAPABILITIES_IGS_WSI: 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 46 case RISCV_IOMMU_CAPABILITIES_IGS_BOTH: 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 47 break; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 48 default: 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 49 return dev_err_probe(dev, -ENODEV, 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 50 "unable to use wire-signaled interrupts\n"); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 51 } 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 52 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 53 iommu->irqs_count = platform_irq_count(pdev); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 @54 if (iommu->irqs_count <= 0) 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 55 return dev_err_probe(dev, -ENODEV, 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 56 "no IRQ resources provided\n"); platform_irq_count() can return -EPROBE_DEFER so iommu->irqs_count needs to be signed. (It's unsigned now). 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 57 if (iommu->irqs_count > RISCV_IOMMU_INTR_COUNT) 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 58 iommu->irqs_count = RISCV_IOMMU_INTR_COUNT; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 59 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 60 for (vec = 0; vec < iommu->irqs_count; vec++) 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 61 iommu->irqs[vec] = platform_get_irq(pdev, vec); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 62 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 63 /* Enable wire-signaled interrupts, fctl.WSI */ 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 64 if (!(iommu->fctl & RISCV_IOMMU_FCTL_WSI)) { 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 65 iommu->fctl |= RISCV_IOMMU_FCTL_WSI; 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 66 riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, iommu->fctl); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 67 } 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 68 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 69 return riscv_iommu_init(iommu); 5c0ebbd3c6c6e0 Tomasz Jeznach 2024-10-15 70 }; -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki