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charset=us-ascii Content-Disposition: inline tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: ea1013c1539270e372fc99854bc6e4d94eaeff66 commit: 4d1608d0ab3365d1ef9447bdbc0cb4c0962f1774 cache: Make top level Kconfig menu a boolean dependent on RISCV date: 4 weeks ago config: riscv-randconfig-r063-20251218 (https://download.01.org/0day-ci/archive/20251218/202512180606.m7eRSrrE-lkp@intel.com/config) compiler: riscv32-linux-gcc (GCC) 12.5.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251218/202512180606.m7eRSrrE-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202512180606.m7eRSrrE-lkp@intel.com/ All errors (new ones prefixed by >>): riscv32-linux-ld: drivers/cache/ax45mp_cache.o: in function `ax45mp_cache_init': >> drivers/cache/ax45mp_cache.c:213:(.init.text+0x104): undefined reference to `riscv_noncoherent_register_cache_ops' Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for AX45MP_L2_CACHE Depends on [n]: CACHEMAINT_FOR_DMA [=n] Selected by [y]: - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] && NONPORTABLE [=y] && !DMA_DIRECT_REMAP [=n] && RISCV_ALTERNATIVE [=y] && !RISCV_ISA_ZICBOM [=n] && RISCV_SBI [=y] vim +213 drivers/cache/ax45mp_cache.c d34599bcd2e4e9 Lad Prabhakar 2023-08-18 178 d34599bcd2e4e9 Lad Prabhakar 2023-08-18 179 static int __init ax45mp_cache_init(void) d34599bcd2e4e9 Lad Prabhakar 2023-08-18 180 { d34599bcd2e4e9 Lad Prabhakar 2023-08-18 181 struct device_node *np; d34599bcd2e4e9 Lad Prabhakar 2023-08-18 182 struct resource res; d34599bcd2e4e9 Lad Prabhakar 2023-08-18 183 int ret; d34599bcd2e4e9 Lad Prabhakar 2023-08-18 184 d34599bcd2e4e9 Lad Prabhakar 2023-08-18 185 np = of_find_matching_node(NULL, ax45mp_cache_ids); d34599bcd2e4e9 Lad Prabhakar 2023-08-18 186 if (!of_device_is_available(np)) d34599bcd2e4e9 Lad Prabhakar 2023-08-18 187 return -ENODEV; d34599bcd2e4e9 Lad Prabhakar 2023-08-18 188 d34599bcd2e4e9 Lad Prabhakar 2023-08-18 189 ret = of_address_to_resource(np, 0, &res); d34599bcd2e4e9 Lad Prabhakar 2023-08-18 190 if (ret) d34599bcd2e4e9 Lad Prabhakar 2023-08-18 191 return ret; d34599bcd2e4e9 Lad Prabhakar 2023-08-18 192 d34599bcd2e4e9 Lad Prabhakar 2023-08-18 193 /* d34599bcd2e4e9 Lad Prabhakar 2023-08-18 194 * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size d34599bcd2e4e9 Lad Prabhakar 2023-08-18 195 * will be 0 for sure, so we can definitely rely on it. If d34599bcd2e4e9 Lad Prabhakar 2023-08-18 196 * riscv_cbom_block_size = 0 we don't need to handle CMO using SW any d34599bcd2e4e9 Lad Prabhakar 2023-08-18 197 * more so we just return success here and only if its being set we d34599bcd2e4e9 Lad Prabhakar 2023-08-18 198 * continue further in the probe path. d34599bcd2e4e9 Lad Prabhakar 2023-08-18 199 */ d34599bcd2e4e9 Lad Prabhakar 2023-08-18 200 if (!riscv_cbom_block_size) d34599bcd2e4e9 Lad Prabhakar 2023-08-18 201 return 0; d34599bcd2e4e9 Lad Prabhakar 2023-08-18 202 d34599bcd2e4e9 Lad Prabhakar 2023-08-18 203 ax45mp_priv.l2c_base = ioremap(res.start, resource_size(&res)); d34599bcd2e4e9 Lad Prabhakar 2023-08-18 204 if (!ax45mp_priv.l2c_base) d34599bcd2e4e9 Lad Prabhakar 2023-08-18 205 return -ENOMEM; d34599bcd2e4e9 Lad Prabhakar 2023-08-18 206 d34599bcd2e4e9 Lad Prabhakar 2023-08-18 207 ret = ax45mp_get_l2_line_size(np); d34599bcd2e4e9 Lad Prabhakar 2023-08-18 208 if (ret) { d34599bcd2e4e9 Lad Prabhakar 2023-08-18 209 iounmap(ax45mp_priv.l2c_base); d34599bcd2e4e9 Lad Prabhakar 2023-08-18 210 return ret; d34599bcd2e4e9 Lad Prabhakar 2023-08-18 211 } d34599bcd2e4e9 Lad Prabhakar 2023-08-18 212 d34599bcd2e4e9 Lad Prabhakar 2023-08-18 @213 riscv_noncoherent_register_cache_ops(&ax45mp_cmo_ops); :::::: The code at line 213 was first introduced by commit :::::: d34599bcd2e4e93a28d5904bf94bc7dafc511f04 cache: Add L2 cache management for Andes AX45MP RISC-V core :::::: TO: Lad Prabhakar :::::: CC: Palmer Dabbelt -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki