From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D340F2DE1E0 for ; Thu, 18 Dec 2025 08:11:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766045496; cv=none; b=HxO+MaCkKaVCcm5/HkbdTyBRLWU8ABp1RzkIx+ttxws+7uCUu4J7568Z9/UIPpXMeQuXSMXNk2MYi729xDWVq/p+A2CToO9mu46mk9tZ0ijaMiB0JACV+YdXt7XkdiG9rCq/uW9F4uqYgmPH+QsW1bqO3tnq1GE5bA/X+9P7n7c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766045496; c=relaxed/simple; bh=tqM3gGG0QcFXXo8kUbIqDxY07VTSw7EPU0yqqlLD/TI=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=o0Lcgi1IdF8FKc01MHw+vsdXiOVlLsEBG4663ARZqlXBU6g1q3gciHGnrK2QbUcX9IEPBe4p5bSCcYMH1w7RB2yWA03GoGYoExYqzmatqV1GlP8Cpa2W9YxGzbYQn19NSMHRlr5qnuvdi/jwr4jAOuCJUnJxqUwGdDmE2uYzIo4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kNrcecZZ; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kNrcecZZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766045495; x=1797581495; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=tqM3gGG0QcFXXo8kUbIqDxY07VTSw7EPU0yqqlLD/TI=; b=kNrcecZZiBb5mEhLbw+vt4ptSaSCqBSFy34t4PgF5yDpAcFm0GQPV2Am cw+6RVvsPuP7kqnRxzW/oY/Mw0ny9KeNON+1vjCOp5j3U2JHn04+ahwh5 ehsxTqU1eWXSYvrceYxYCkPzKypB7RXXSbRncZoMFbf+NxtmVn/VuhNI8 kgpBHaIdSKg+LO3ojTyJLFUPoASWxu5ncmjAmQd7z02Fr8/NSZsADIjNa obwOJ1NL2EFtXvBnRWHTazSveCTzwuxkNwLW1zyqHkl0KPmnKAyn4SpGY Lga5/tJCu8vLuLMfF0dT5TjH3m2jOpbsyI20WH16gT5kR9GjhoxzmSGJq Q==; X-CSE-ConnectionGUID: f4ALNutJTsekmbjWSsT2tw== X-CSE-MsgGUID: 4YoA4frmQ/6UoOCNdhsrBg== X-IronPort-AV: E=McAfee;i="6800,10657,11645"; a="67873791" X-IronPort-AV: E=Sophos;i="6.21,156,1763452800"; d="scan'208";a="67873791" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Dec 2025 00:11:34 -0800 X-CSE-ConnectionGUID: dx58pOvuTW2c7W7dOR9y9Q== X-CSE-MsgGUID: gSvbGOF7RQa7zNY506lPdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,156,1763452800"; d="scan'208";a="198779777" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.22]) by fmviesa008.fm.intel.com with ESMTP; 18 Dec 2025 00:11:32 -0800 From: Xiaoyao Li To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , Tony Luck , linux-kernel@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH 0/2] x86/split_lock: Fix and cleanup of cpu_model_supports_sld Date: Thu, 18 Dec 2025 16:00:42 +0800 Message-ID: <20251218080044.2615106-1-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit While considering Kiryl's suggestion[1], I'm wondering why we have cpu_model_supports_sld defined, which seems like it could be replaced by X86_FEATURE_SPLIT_LOCK_DETECT. Tracing through the history, I find that X86_FEATURE_SPLIT_LOCK_DETECT originally indicated whether the kernel enabled the split lock detection feature, rather than enumerating hardware support for the feature, at the time when cpu_model_supports_sld was introduced. Now, the semantics of X86_FEATURE_SPLIT_LOCK_DETECT have changed and it enuemrates the hardware support for the feature. Therefore, patch 2 replaces cpu_model_supports_sld with X86_FEATURE_SPLIT_LOCK_DETECT. Patch 1 fixes a potential issue where MSR_TEST_CTRL can be written when the split lock detection feature is not available, which can cause bizarre behavior. [1] https://lore.kernel.org/all/lvobu4gpfsjg63syubgy2jwcja72folflrst7bu2eqv6rhaqre@ttbkykphu32f/ Xiaoyao Li (2): x86/split_lock: Fix handling in split_lock_init() x86/split_lock: Drop cpu_model_supports_sld arch/x86/kernel/cpu/bus_lock.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) -- 2.43.0