From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx-relay10-hz2.antispameurope.com (mx-relay10-hz2.antispameurope.com [83.246.65.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F78E3559D5 for ; Thu, 18 Dec 2025 15:22:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=83.246.65.96 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766071338; cv=pass; b=Fw+OwcZ5jC6o69yqPGn7KJYDZxQ39GGNtAaf24RJiNUJyugYRMyRMoYlSJnEzQlryl+fBCuDezV0TzJ89DhSrbRpkzHD+4F4R0GE1KtaOGgHQiyWvkL1qpx2ig7m+/fyHo+9xhbQjCZrdk2N3enbXLmSJyDudhaOet1Ju3VnClE= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766071338; c=relaxed/simple; bh=XQ46J/0Q/s1txq+6yOGv2tGq9CYnPBG5axSq5J5swGE=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=OcZyl0OZzSVMnZ0vGxLQOFkw/6B+KjyNfdrn5IYF556yqFNPYZgNVVpNZVui65e9psczeeOQh2efChYUUvYDc5ClK9L/moAsj663Iyzd9AAM4IBaiee8KmrNZojk1kXI+LhBS14eLWTm7VTsuXXKkobrf/CDPm3WASC+VERCLEk= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=gDIDQDRk; arc=pass smtp.client-ip=83.246.65.96 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="gDIDQDRk" ARC-Authentication-Results: i=1; mx-gate10-hz2.hornetsecurity.com 1; spf=pass reason=mailfrom (ip=94.100.132.6, headerfrom=ew.tq-group.com) smtp.mailfrom=ew.tq-group.com smtp.helo=hmail-p-smtp01-out03-hz1.hornetsecurity.com; dmarc=pass header.from=ew.tq-group.com orig.disposition=pass ARC-Message-Signature: a=rsa-sha256; bh=7AMuBMEfhIQw9FVyiKx57RUqUljgR4wYmPvn8hqi5T4=; c=relaxed/relaxed; d=hornetsecurity.com; h=from:to:date:subject:mime-version:; i=1; s=hse1; t=1766071300; b=qpjB6DLDsCOCumI1zK8phBcdmxvR9u+oILFjg7v3E+Kmg8enicXA6/eEBJCUckGu9VcVbcQW D45pQ0twUNV6SrOWGTiWgjJznJOYYm8pAp3hZvJ+UhoYgxEkHuq1AgzX6bjY5f81kdv2my/e3f3 xzWY6qD2xVHfHN4BeWBU5ghDIIOQB/HLqnf/jDEzxxfq06oYiUx50BIokGQl5skUvgiLQbj2NJV qwpiiBXs/vr3cq4OoRUwnsktCSeWNyUl6+j7uc4B3PJ491dhkNoTSvdRVm3wKqh25iGqcfJhsaT /ogvhNnrmvT885R+DUPwWQKRze0ZGKjKnzxLrDXe8Vmxw== ARC-Seal: a=rsa-sha256; cv=none; d=hornetsecurity.com; i=1; s=hse1; t=1766071300; b=S7ddgKCFoAA0SYcEQV7/7Q/lUb/mYE0uRvGwM9PHMlRzQOJJkmgUgakhwNgt2TPbyNIMv03a iptelJD8BoFwcKxQO3Lvx9ruawOmOX2si9XwX+OczmiF/LgfXTs2VeH2q7ecML9VbaReavDeuh2 RVAsUOv19COOCGpLfOERqJrqegSuh08+v4fRwD63tMc1rfi2CFGCQ8wVifMu5wdjOPDRNHfmZTK A4Lz6aUOY31a/ozZnIZN+VSh94Q9GlfKQWwvl0MWV4ng2h84FoE8z+kXwNo31ws9teMylKXUvTA gRAEJIWFE5QfdjysGQhyFfrejvYLiX2ZlqWF0OM9eiBVQ== Received: from he-nlb01-hz1.hornetsecurity.com ([94.100.132.6]) by mx-relay10-hz2.antispameurope.com; Thu, 18 Dec 2025 16:21:39 +0100 Received: from steina-w.tq-net.de (host-82-135-125-110.customer.m-online.net [82.135.125.110]) (Authenticated sender: alexander.stein@ew.tq-group.com) by hmail-p-smtp01-out03-hz1.hornetsecurity.com (Postfix) with ESMTPSA id 16D9ACC0D31; Thu, 18 Dec 2025 16:21:04 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Peter Chen , Pawel Laszczak , Roger Quadros , Greg Kroah-Hartman , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Magnus Damm , Marek Vasut Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-usb@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com Subject: [PATCH 0/6] Support TQMa8QM Date: Thu, 18 Dec 2025 16:20:47 +0100 Message-ID: <20251218152058.1521806-1-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-cloud-security-sender:alexander.stein@ew.tq-group.com X-cloud-security-recipient:linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: alexander.stein@ew.tq-group.com X-cloud-security-Mailarchivtype:outbound X-cloud-security-Virusscan:CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay10-hz2.antispameurope.com with 4dXDrx4SHSz4F929 X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest:836eb70413c5acce62e457440dd9da8d X-cloud-security:scantime:4.420 DKIM-Signature: a=rsa-sha256; bh=7AMuBMEfhIQw9FVyiKx57RUqUljgR4wYmPvn8hqi5T4=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1766071299; v=1; b=gDIDQDRkJ5OuR+4kIGku59wMUet/UrNyYnD5xcCNw8WhAGN4S772vu/QChoDhT6NVzfdmmDH HiDAnx7PUTUERh0OVT23/luVsKNfcv5K/qKfWzp4XPJAEFu2GWs0eOlYVHRpyiaMp0jrYXm8q12 EUQ+S+zw1o2Q/wJQu2Y8GJDHmlyR/wSIIVRK6wBgLDHKglcEmIA9UL3kWyvxbvNRDDLfRb2fObe lXpuLhqLpmh6O4/hgrLl4T5OIjmluD6+MwLX+et6U+0cI9K9j23y2QMOAFFL5vriz2vaBhM7Aln IFaMZJ+iYZEZpMFF44Z7CyfE3Sd/7GDmHsPKr8+HRLstg== Hi, this series adds support for TQ's TQMa8QM. The first 3 patches are prepatory: 1. Add support for clock-output-names for clk-renesas-pcie. This is necessary as clk-imx8qxp-lpcg.c (driver for phyx1 phyx2 clock gating) reqiures that property on the parent clock. 2. Add support for USB devices in cdns USB3 host controller, namely onboard-devices as USB hubs. Implemented similarily to snps,dwc3-common.yaml. 3. Add DMA IRQ for PCIe controller. Similar to commit 0b4c46f9ad79c ("arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe") which was only tested on imx8qxp which just has one PCIe controller. 4 & 5. Device bindings and platform DT 6. Workaround for missing "ERR050104: Arm/A53: Cache coherency issue" workaround. See [1] for details. Split into separate commit for easy revert once an errata workaround has been integrated. Best regards, Alexander [1] https://lore.kernel.org/all/20230420112952.28340-1-iivanov@suse.de/ Alexander Stein (6): dt-bindings: clk: rs9: add clock-output-names property dt-bindings: usb: cdns,usb3: support USB devices in DT arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe dt-bindings: arm: fsl: add bindings for TQMa8x arm64: dts: Add TQ imx8qm based board arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster .../devicetree/bindings/arm/fsl.yaml | 10 + .../bindings/clock/renesas,9series.yaml | 37 + .../devicetree/bindings/usb/cdns,usb3.yaml | 11 + arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 5 +- .../dts/freescale/imx8qm-tqma8qm-mba8x.dts | 869 ++++++++++++++++++ .../boot/dts/freescale/imx8qm-tqma8qm.dtsi | 322 +++++++ 7 files changed, 1253 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi -- 2.43.0