From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sg-1-100.ptr.blmpb.com (sg-1-100.ptr.blmpb.com [118.26.132.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A22E223B63F for ; Fri, 19 Dec 2025 03:20:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=118.26.132.100 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766114445; cv=none; b=XhfkxrZMViQ6HwprCnwrL+nUHWvXBkwvC1rpw0qySCABPuC1dEUsS/rU9DTwpqDH5qLF5rtwNCqVkpxljOPDv61ne6MLKp5VhIuTCqfmlol+WkKgGBvCyUkqx+dZuxfph+iFgSjd19u2BIGqUa0xEnx9psaP70ZR8EcAEoVP1Wc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766114445; c=relaxed/simple; bh=ZdBUVVGNZwggrafWqO4GgClNw6CLeIf7GrxNpREiqv0=; h=Cc:Message-Id:Mime-Version:From:Content-Type:Content-Disposition: To:Subject:Date:References:In-Reply-To; b=d1hMfqe3Th/+5SRTg9XYeu7R2mOgzBzfFxsKu371mx0+Mw7IlnoiVW4nskCt57V2qyWmdvvCHkAA+HjQsdkGF+fNUNETMVr4DSBJTSJt4LUoVK5+Cm9XXpUI7rLYjrf8wtWQCr3O6vPwdgdQiBh1xOXfhfW6NObDJIxyFz8nf+o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=L11PZYzz; arc=none smtp.client-ip=118.26.132.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="L11PZYzz" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=2212171451; d=bytedance.com; t=1766114428; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=Wgle8V/RnjyJ4S6SpFrrSmwlnY8vUPyKwh7T20p7EXU=; b=L11PZYzzfizE07H2i3MbZSGtu8REiXiqhy8jELj3Pbzk0SfG/Ob6l5yM0mQ+84wqJDADWe ewovFOpbIKTc4pfG8B+tDhZBlOGjhT1K5e1jnAAFgrjpL6tkY91dMmHAvfS+JFh9piK96Y PSQN3rDI8RTJ5G2dustoi0pPvkjChse0OAmgI4l/V42GhS+BN9S5B0kgN+/eLU7FduYnEj 5oJgRdh0mcBbTn+kKYDYlkobOLIGrZNgZMsZOl8dhSYl3qj1CC/7Y62W96z9uS0bqSU3Xa GBa3ywtATSc/H2SD6Y0PYQlSrGCov4tsRJADEyqyfqljUTowEzS9pz2S+Mn2cg== X-Lms-Return-Path: Cc: "Peter Zijlstra" , "Ingo Molnar" , "K Prateek Nayak" , "Gautham R . Shenoy" , "Vincent Guittot" , "Juri Lelli" , "Dietmar Eggemann" , "Steven Rostedt" , "Ben Segall" , "Mel Gorman" , "Valentin Schneider" , "Madadi Vineeth Reddy" , "Hillf Danton" , "Shrikanth Hegde" , "Jianyong Wu" , "Yangyu Chen" , "Tingyin Duan" , "Vern Hao" , "Vern Hao" , "Len Brown" , "Aubrey Li" , "Zhao Liu" , "Chen Yu" , "Chen Yu" , "Adam Li" , "Tim Chen" , Message-Id: <20251219031952.GA2598944@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Original-From: Aaron Lu From: "Aaron Lu" Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable To: "Tim Chen" Subject: Re: [PATCH v2 00/23] Cache aware scheduling Date: Fri, 19 Dec 2025 11:19:52 +0800 References: In-Reply-To: On Wed, Dec 03, 2025 at 03:07:19PM -0800, Tim Chen wrote: ... ... > Test results: >=20 > The patch series was applied and tested on v6.18-rc7. > See: https://github.com/timcchen1298/linux/commits/cache_aware_v2 >=20 > The first test platform is a 2 socket Intel Sapphire Rapids with 30 > cores per socket. The DRAM interleaving is enabled in the BIOS so it > essential has one NUMA node with two last level caches. There are 60 > CPUs associated with each last level cache. >=20 > The second test platform is a AMD Genoa. There are 4 Nodes and 32 CPUs > per node. Each node has 2 CCXs and each CCX has 16 CPUs. >=20 > hackbench/schbench/netperf/stream/stress-ng/chacha20 were launched on > these two platforms. >=20 > [TL;DR] > Sappire Rapids: > hackbench shows significant improvement when the number of > different active threads is below the capacity of a LLC. > schbench shows overall wakeup latency improvement. > ChaCha20-xiangshan shows good throughput improvement. >=20 > Genoa: > ChaCha20-xiangshan shows huge throughput improvement. > No obvious difference is observed in hackbench/schbench I think for small task number hackbench run, there should be some improvement. I tried thread/pipe/2fds/1group, i.e. 4 tasks on Genoa: ./hackbench -T -f 2 -g 1 -p -l 2000000 And I noticed performance improved a lot: (Result in seconds, less is better) llc_off llc_on diff time 4.755=C2=B11.6% 2.684=C2=B16.25% +43.6% llc_off means /sys/kernel/debug/sched/llc_enabled set to 0 while llc_on means /sys/kernel/debug/sched/llc_enabled set to 1, other tunnables are left unchanged. Turbo is disabled and cpufreq set to performance. I also tried redis and noticed when I set io-threads to 4 in redis.conf, there is also some improvement on AMD Genoa: llc_off manual diff llc_on diff throughput 1536727=C2=B10% 1737619=C2=B10% +13.1% 1737720=C2=B1= 0% +13.1% Client cmdline: numactl -N 1 redis-benchmark --threads 4 -t set -r 100000 -P 16 -n 10000000 server cmdline: numactl -N 0 redis-server ./redis.conf I also tried to manually bind all tasks of redis server to a single LLC to see if this workload benefits from aggregation and that's what manual means: taskset -c 8-15,200-207 redis-server ./redis.conf According to the result, I think this 'cache aware scheduling' works as expected in that its performance is the same as manual binding; and they all beat llc_off.