From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sg-1-102.ptr.blmpb.com (sg-1-102.ptr.blmpb.com [118.26.132.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D6AC1A2630 for ; Fri, 19 Dec 2025 03:32:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=118.26.132.102 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766115167; cv=none; b=JKkmPL01oq1Q/PUjB0EAcojCyNOT6x+47pupZH4k5zMIplYtvA5fLrkk0tWPNpmzwg+RHCaehZ7xy/NsnJooeST4laLAXSwyajbGdul5hSdf/xADx6d3WkvXaGsdtqU2MzHfIZ1jBoQPBS3QhbTxXCjZq/ivUCsdI9uXQiCqbmU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766115167; c=relaxed/simple; bh=7/1uZJIOP1A1LLd1Ssa9TW1DIO6Y9peEWtDls5huWTQ=; h=To:Date:Message-Id:References:Content-Disposition:From:Subject: Content-Type:Cc:Mime-Version:In-Reply-To; b=bJrqO4a/NVK4zXWxspWl1nTKY5YYSBjWME2Pi4iw5RSXH/PDzkaISfHGJBS7cHTl5d7uZ0zFcf13VeJcG8QK8gPEhy8tuL9Xwd/m13SPu/0sh6sQlXHiijrRRnx+wAwZjFAFqFsmzPClPwbPm4zfdlXAp50pjDTbcLBnUmKEWXQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=FWMYSwa5; arc=none smtp.client-ip=118.26.132.102 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="FWMYSwa5" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=2212171451; d=bytedance.com; t=1766115151; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=XP5qdHzO3HkW1IQmfSjkrIM9SIMZf0wWn+VR4YLZlYU=; b=FWMYSwa5wney64/0n8vEW90usp1Gn3fXApp+EpZPwP6wFuy9CGnGsJZ+fpekntgWAwVbaz /NPbiNxw/B/f7G+suZYzlbolteQ+nXzbg36JafOjMuBaG+zCz12f/63yaKKrOKf5bOgsOx DUiUnmGZQIdmjKjNmOG7fYNsZsM+Ny1/wL0/QrhgPT3jgBs2lCjzBrulE4UwGkcSwybS+Y AesCY123CZOCC64OCxyeyWcw6trNmyMsugk8lYiqz3twOoiGfKXYbRFu8pCDH8lPadhJ4K /SoR1r7/ZHMLhEo2pZCERv8b1FyVUENosUQxnUuDTRO8wLN9cmgVEZ7GPRR49g== To: "Chen, Yu C" Date: Fri, 19 Dec 2025 11:32:04 +0800 Message-Id: <20251219033204.GB2598944@bytedance.com> References: <20251217094053.GA2073381@bytedance.com> <61b1242b-59a8-42ea-a6a5-813fa063f0fd@intel.com> X-Lms-Return-Path: X-Original-From: Aaron Lu Content-Disposition: inline Content-Transfer-Encoding: 7bit From: "Aaron Lu" Subject: Re: [PATCH v2 17/23] sched/cache: Record the number of active threads per process for cache-aware scheduling Content-Type: text/plain; charset=UTF-8 Cc: "Peter Zijlstra" , "Ingo Molnar" , "K Prateek Nayak" , "Gautham R . Shenoy" , "Vincent Guittot" , "Juri Lelli" , "Dietmar Eggemann" , "Steven Rostedt" , "Ben Segall" , "Mel Gorman" , "Valentin Schneider" , "Madadi Vineeth Reddy" , "Hillf Danton" , "Shrikanth Hegde" , "Jianyong Wu" , "Yangyu Chen" , "Tingyin Duan" , "Vern Hao" , "Vern Hao" , "Len Brown" , "Aubrey Li" , "Zhao Liu" , "Chen Yu" , "Adam Li" , "Tim Chen" , , "Tim Chen" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 In-Reply-To: <61b1242b-59a8-42ea-a6a5-813fa063f0fd@intel.com> On Wed, Dec 17, 2025 at 08:51:50PM +0800, Chen, Yu C wrote: > On 12/17/2025 5:40 PM, Aaron Lu wrote: > > On Wed, Dec 03, 2025 at 03:07:36PM -0800, Tim Chen wrote: > > > @@ -1501,6 +1507,7 @@ static void __no_profile task_cache_work(struct callback_head *work) > > > mm->mm_sched_cpu = m_a_cpu; > > > } > > > + update_avg(&mm->nr_running_avg, nr_running); > > > > update_avg() doesn't appear to deal with small numbers well and can have > > an error as large as 7, e.g. when nr_running < 8, nr_running_avg will > > always be 0 and when nr_running >= 8 && < 16, nr_running_avg will be > > 1 - 8, etc. > > > > AMD Genoa has 8 cores per LLC and this will break exceed_llc_nr() there. > > > > Ah, you are right, thanks for pointing this out, dividing by 8 would make > convergence slow for small LLC system. Maybe consider the number of Cores Not just slow but the error is too large for a small LLC. > in the LLC, the smaller the number is, the more we should honor the diff > between two invoking of update_avg()? > > static inline void sched_cache_update_avg(u64 *avg, u64 sample) > { > s64 diff = sample - *avg; > u32 divisor = clamp_t(u32, nr_cores_llc/4, 2, 8); > > *avg += diff / divisor; > } > > For <=8 cores per LLC, the divisor is 2, > for 16 cores per LLC, the divisor is 4, > for >=32 cores per LLC, the divisor is 8 Yeah I guess it works. The error can be as large as 'divisor - 1' but since this avg is an estimate, it may be OK.