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Thu, 18 Dec 2025 21:37:10 -0800 (PST) Received: from Barrys-MBP.hub ([47.72.129.29]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d4d895sm9930215ad.54.2025.12.18.21.37.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Dec 2025 21:37:09 -0800 (PST) From: Barry Song <21cnbao@gmail.com> To: catalin.marinas@arm.com, m.szyprowski@samsung.com, robin.murphy@arm.com, will@kernel.org Cc: ada.coupriediaz@arm.com, anshuman.khandual@arm.com, ardb@kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, ryan.roberts@arm.com, surenb@google.com, v-songbaohua@oppo.com, zhengtangquan@oppo.com Subject: [PATCH 0/6] dma-mapping: arm64: support batched cache sync Date: Fri, 19 Dec 2025 13:36:52 +0800 Message-Id: <20251219053658.84978-1-21cnbao@gmail.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Barry Song Many embedded ARM64 SoCs still lack hardware cache coherency support, which causes DMA mapping operations to appear as hotspots in on-CPU flame graphs. For an SG list with *nents* entries, the current dma_map/unmap_sg() and DMA sync APIs perform cache maintenance one entry at a time. After each entry, the implementation synchronously waits for the corresponding region’s D-cache operations to complete. On architectures like arm64, efficiency can be improved by issuing all entries’ operations first and then performing a single batched wait for completion. Tangquan's results show that batched synchronization can reduce dma_map_sg() time by 64.61% and dma_unmap_sg() time by 66.60% on an MTK phone platform (MediaTek Dimensity 9500). The tests were performed by pinning the task to CPU7 and fixing the CPU frequency at 2.6 GHz, running dma_map_sg() and dma_unmap_sg() on 10 MB buffers (10 MB / 4 KB sg entries per buffer) for 200 iterations and then averaging the results. I also ran this patch set on an RK3588 Rock5B+ board and observed that millions of DMA sync operations were batched. diff with RFC: * Dropped lots of #ifdef/#else/#endif according to Catalin and Marek, thanks! * Also add iova link/unlink batches, which is marked as RFC as i lack hardware. This is suggested by Marek, thanks! RFC link: https://lore.kernel.org/lkml/20251029023115.22809-1-21cnbao@gmail.com/ Barry Song (6): arm64: Provide dcache_by_myline_op_nosync helper arm64: Provide dcache_clean_poc_nosync helper arm64: Provide dcache_inval_poc_nosync helper arm64: Provide arch_sync_dma_ batched helpers dma-mapping: Allow batched DMA sync operations if supported by the arch dma-iommu: Allow DMA sync batching for IOVA link/unlink arch/arm64/Kconfig | 1 + arch/arm64/include/asm/assembler.h | 79 +++++++++++++++++++------- arch/arm64/include/asm/cacheflush.h | 2 + arch/arm64/mm/cache.S | 58 +++++++++++++++---- arch/arm64/mm/dma-mapping.c | 24 ++++++++ drivers/iommu/dma-iommu.c | 12 +++- include/linux/dma-map-ops.h | 22 ++++++++ kernel/dma/Kconfig | 3 + kernel/dma/direct.c | 28 +++++++--- kernel/dma/direct.h | 86 +++++++++++++++++++++++++---- 10 files changed, 262 insertions(+), 53 deletions(-) -- 2.39.3 (Apple Git-146)