From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: pbonzini@redhat.com, seanjc@google.com
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
chao.gao@intel.com, chang.seok.bae@intel.com
Subject: [PATCH 16/16] KVM: x86: selftests: Add APX state handling and XCR0 sanity checks
Date: Sun, 21 Dec 2025 04:07:42 +0000 [thread overview]
Message-ID: <20251221040742.29749-17-chang.seok.bae@intel.com> (raw)
In-Reply-To: <20251221040742.29749-1-chang.seok.bae@intel.com>
Now that KVM exposes the APX feature to guests on APX-capable systems,
extend the selftests to validate XCR0 configuration and state management.
Since APX repurposes the XSAVE area previously used by MPX in the
non-compacted format, add a check to ensure that MPX states are not set
when APX is enabled.
Also, load non-init APX state data in the guest so that XSTATE_BV[APX] is
set, allowing validation of APX state testing.
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
---
No change since last version
---
.../selftests/kvm/include/x86/processor.h | 1 +
tools/testing/selftests/kvm/x86/state_test.c | 6 ++++++
.../selftests/kvm/x86/xcr0_cpuid_test.c | 19 +++++++++++++++++++
3 files changed, 26 insertions(+)
diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/testing/selftests/kvm/include/x86/processor.h
index 57d62a425109..6a1da26780ea 100644
--- a/tools/testing/selftests/kvm/include/x86/processor.h
+++ b/tools/testing/selftests/kvm/include/x86/processor.h
@@ -88,6 +88,7 @@ struct xstate {
#define XFEATURE_MASK_LBR BIT_ULL(15)
#define XFEATURE_MASK_XTILE_CFG BIT_ULL(17)
#define XFEATURE_MASK_XTILE_DATA BIT_ULL(18)
+#define XFEATURE_MASK_APX BIT_ULL(19)
#define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \
XFEATURE_MASK_ZMM_Hi256 | \
diff --git a/tools/testing/selftests/kvm/x86/state_test.c b/tools/testing/selftests/kvm/x86/state_test.c
index f2c7a1c297e3..2b7aa4cca011 100644
--- a/tools/testing/selftests/kvm/x86/state_test.c
+++ b/tools/testing/selftests/kvm/x86/state_test.c
@@ -167,6 +167,12 @@ static void __attribute__((__flatten__)) guest_code(void *arg)
asm volatile ("vmovupd %0, %%zmm16" :: "m" (buffer));
}
+ if (supported_xcr0 & XFEATURE_MASK_APX) {
+ /* mov $0xcccccccc, %r16 */
+ asm volatile (".byte 0xd5, 0x18, 0xb8, 0xcc, 0xcc,"
+ "0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00");
+ }
+
if (this_cpu_has(X86_FEATURE_MPX)) {
uint64_t bounds[2] = { 10, 0xffffffffull };
uint64_t output[2] = { };
diff --git a/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c b/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
index d038c1571729..e3d3af5ab6f2 100644
--- a/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
+++ b/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
@@ -46,6 +46,20 @@ do { \
__supported, (xfeatures)); \
} while (0)
+/*
+ * Verify that mutually exclusive architectural features do not overlap.
+ * For example, APX and MPX must never be reported as supported together.
+ */
+#define ASSERT_XFEATURE_CONFLICT(supported_xcr0, xfeatures, conflicts) \
+do { \
+ uint64_t __supported = (supported_xcr0) & ((xfeatures) | (conflicts)); \
+ \
+ __GUEST_ASSERT((__supported & (xfeatures)) != (xfeatures) || \
+ !(__supported & (conflicts)), \
+ "supported = 0x%lx, xfeatures = 0x%llx, conflicts = 0x%llx", \
+ __supported, (xfeatures), (conflicts)); \
+} while (0)
+
static void guest_code(void)
{
uint64_t initial_xcr0;
@@ -79,6 +93,11 @@ static void guest_code(void)
ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0,
XFEATURE_MASK_XTILE);
+ /* Check APX by ensuring MPX is not exposed concurrently */
+ ASSERT_XFEATURE_CONFLICT(supported_xcr0,
+ XFEATURE_MASK_APX,
+ XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
+
vector = xsetbv_safe(0, XFEATURE_MASK_FP);
__GUEST_ASSERT(!vector,
"Expected success on XSETBV(FP), got %s",
--
2.51.0
next prev parent reply other threads:[~2025-12-21 4:31 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-21 4:07 [PATCH 00/16] KVM: x86: Enable APX for guests Chang S. Bae
2025-12-21 4:07 ` [PATCH 01/16] KVM: x86: Rename register accessors to be GPR-specific Chang S. Bae
2025-12-21 4:07 ` [PATCH 02/16] KVM: x86: Refactor GPR accessors to differentiate register access types Chang S. Bae
2025-12-21 4:07 ` [PATCH 03/16] KVM: x86: Implement accessors for extended GPRs Chang S. Bae
2025-12-22 14:23 ` Paolo Bonzini
2025-12-21 4:07 ` [PATCH 04/16] KVM: VMX: Introduce unified instruction info structure Chang S. Bae
2025-12-21 4:07 ` [PATCH 05/16] KVM: VMX: Refactor instruction information retrieval Chang S. Bae
2025-12-21 4:07 ` [PATCH 06/16] KVM: VMX: Refactor GPR index retrieval from exit qualification Chang S. Bae
2025-12-21 4:07 ` [PATCH 07/16] KVM: nVMX: Propagate the extended instruction info field Chang S. Bae
2025-12-31 1:38 ` Chao Gao
2025-12-21 4:07 ` [PATCH 08/16] KVM: VMX: Support extended register index in exit handling Chang S. Bae
2025-12-26 5:27 ` Chao Gao
2025-12-21 4:07 ` [PATCH 09/16] KVM: emulate: Support EGPR accessing and tracking Chang S. Bae
2025-12-21 4:07 ` [PATCH 10/16] KVM: emulate: Handle EGPR index and REX2-incompatible opcodes Chang S. Bae
2025-12-22 14:36 ` Paolo Bonzini
2025-12-21 4:07 ` [PATCH 11/16] KVM: emulate: Support REX2-prefixed opcode decode Chang S. Bae
2025-12-21 4:07 ` [PATCH 12/16] KVM: emulate: Reject EVEX-prefixed instructions Chang S. Bae
2025-12-21 4:07 ` [PATCH 13/16] KVM: x86: Guard valid XCR0.APX settings Chang S. Bae
2025-12-21 4:07 ` [PATCH 14/16] KVM: x86: Expose APX foundational feature bit to guests Chang S. Bae
2025-12-21 4:07 ` [PATCH 15/16] KVM: x86: Expose APX sub-features " Chang S. Bae
2025-12-21 4:07 ` Chang S. Bae [this message]
2025-12-22 14:53 ` [PATCH 00/16] KVM: x86: Enable APX for guests Paolo Bonzini
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