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charset=us-ascii tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: ccd1cdca5cd433c8a5dff78b69a79b31d9b77ee1 commit: e6a8a000cfe6a1106c17ab4a47eb6dd21596968c drm/amd/display: Rename dml2 to dml2_0 folder date: 8 weeks ago config: i386-randconfig-063-20251221 (https://download.01.org/0day-ci/archive/20251225/202512250637.YJF49yZb-lkp@intel.com/config) compiler: gcc-14 (Debian 14.2.0-19) 14.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251225/202512250637.YJF49yZb-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202512250637.YJF49yZb-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c:418:87: sparse: sparse: Using plain integer as NULL pointer drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c:418:90: sparse: sparse: Using plain integer as NULL pointer -- drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:7192:56: sparse: sparse: symbol 'core_dcn4_g6_temp_read_blackout_table' was not declared. Should it be static? >> drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:11176:73: sparse: sparse: Using plain integer as NULL pointer drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:11177:69: sparse: sparse: Using plain integer as NULL pointer drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:11735:74: sparse: sparse: Using plain integer as NULL pointer drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:11736:70: sparse: sparse: Using plain integer as NULL pointer vim +418 drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 390 be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 391 /* be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 392 * For a given set of pipe start/end x positions, checks to see it can support the input mcache splitting. be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 393 * It also attempts to "optimize" by finding a shift if the default 0 shift does not work. be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 394 */ be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 395 static bool find_shift_for_valid_cache_id_assignment(int *mcache_boundaries, unsigned int num_boundaries, be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 396 int *pipe_vp_startx, int *pipe_vp_endx, unsigned int pipe_count, int shift_granularity, int *shift) be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 397 { be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 398 int max_shift = 0xFFFF; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 399 unsigned int pipe_index; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 400 unsigned int i, slice_width; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 401 bool success = false; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 402 be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 403 for (i = 0; i < num_boundaries; i++) { be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 404 if (i == 0) be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 405 slice_width = mcache_boundaries[i]; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 406 else be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 407 slice_width = mcache_boundaries[i] - mcache_boundaries[i - 1]; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 408 be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 409 if (max_shift > (int)slice_width) { be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 410 max_shift = slice_width; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 411 } be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 412 } be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 413 be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 414 for (*shift = 0; *shift <= max_shift; *shift += shift_granularity) { be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 415 success = true; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 416 for (pipe_index = 0; pipe_index < pipe_count; pipe_index++) { be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 417 if (!calculate_first_second_splitting(mcache_boundaries, num_boundaries, *shift, be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 @418 pipe_vp_startx[pipe_index], pipe_vp_endx[pipe_index], 0, 0)) { be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 419 success = false; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 420 break; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 421 } be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 422 } be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 423 if (success) be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 424 break; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 425 } be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 426 be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 427 return success; be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 428 } be4e3509314af7 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c Austin Zheng 2024-11-25 429 :::::: The code at line 418 was first introduced by commit :::::: be4e3509314af751f08677f428f93c306aaa2f8e drm/amd/display: DML21 Reintegration For Various Fixes :::::: TO: Austin Zheng :::::: CC: Alex Deucher -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki