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Thu, 25 Dec 2025 02:06:49 -0800 (PST) Received: from localhost ([2001:19f0:ac00:4eb8:5400:5ff:fe30:7df3]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fe99410sm55195962eec.2.2025.12.25.02.06.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Dec 2025 02:06:49 -0800 (PST) From: Inochi Amaoto To: Bjorn Helgaas , Chen Wang , Inochi Amaoto , Han Gao , Manivannan Sadhasivam Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports Date: Thu, 25 Dec 2025 18:05:27 +0800 Message-ID: <20251225100530.1301625-1-inochiama@gmail.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") force enable ASPM on all device tree platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s and L1 capabilities without supporting it. Override the L0s and L1 Support advertised in Link Capabilities by the SG2042/SG2044 Root Ports so we don't try to enable those states. Inochi Amaoto (2): PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports drivers/pci/quirks.c | 2 ++ include/linux/pci_ids.h | 2 ++ 2 files changed, 4 insertions(+) -- 2.52.0