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Wed, 31 Dec 2025 00:45:47 -0800 (PST) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c1e7a018eb5sm31356070a12.16.2025.12.31.00.45.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Dec 2025 00:45:47 -0800 (PST) From: Akhil P Oommen Subject: [PATCH v6 0/8] Support for Adreno 612 GPU - Respin Date: Wed, 31 Dec 2025 14:15:21 +0530 Message-Id: <20251231-qcs615-spin-2-v6-0-da87debf6883@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAKHiVGkC/3XOzW6DMAwH8FdBOS/ICU6AnvYe0w75XCOtUBIab ap496V0Uis2LrH+lv1zriS5GFwih+pKosshhXEoQb5UxBzV8OFosCUTDlwwYIJOJslS0jkMlFN nUWiwTvd9R8rOOTofvlbv7f2eo5suhZ3vTaJVctSMp1OYD1WWNetpNJzcho8hzWP8Xv+S2Tr9e 7bdnM2MAgWtFKLvoAfxOqZUTxf1eZPr8qxg5g+EwR+EF0Rx2xr02ksnd5DmCeF8izQF6T1aNF3 rBbM7CD4QDrhFsCBeKAAjtJSN30HEE8LlFhEFaQTaTqIEY/Q/yLIsP5dGA53yAQAA X-Change-ID: 20251015-qcs615-spin-2-ed45b0deb998 To: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Jessica Zhang , Gaurav Kohli Cc: Dan Carpenter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang , Akhil P Oommen , Dmitry Baryshkov , Krzysztof Kozlowski , Krzysztof Kozlowski , Qingqing Zhou , Konrad Dybcio , Jie Zhang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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In this version, we have consolidated the previously separate series for DT and driver support, along with some significant rework. Regarding A612 GPU, it falls under ADRENO_6XX_GEN1 family and is a cut down version of A615 GPU. A612 has a new IP called Reduced Graphics Management Unit or RGMU, a small state machine which helps to toggle GX GDSC (connected to CX rail) to implement the IFPC feature. Unlike a full-fledged GMU, the RGMU does not support features such as clock control, resource voting via RPMh, HFI etc. Therefore, we require linux clock driver support similar to gmu-wrapper implementations to control gpu core clock and GX GDSC. In this series, the description of RGMU hardware in devicetree is more complete than in previous version. However, the RGMU core is not initialized from the driver as there is currently no need for it. We do perform a dummy load of RGMU firmware (now available in linux-firmware) to ensure that enabling RGMU core in the future won't break backward compatibility for users. Due to significant changes compared to the old series, all R-b tags have been dropped. Please review with fresh eyes. Last 3 patches are for Bjorn and the rest are for Rob Clark for pick up. [1] Driver: https://lore.kernel.org/lkml/20241213-a612-gpu-support-v3-1-0e9b25570a69@quicinc.com/ Devicetree: https://lore.kernel.org/lkml/fu4rayftf3i4arf6l6bzqyzsctomglhpiniljkeuj74ftvzlpo@vklca2giwjlw/ Signed-off-by: Akhil P Oommen --- Changes in v6: - Move the rgmu register range update from patch#8 to patch#6. - Capture trailers - Link to v5: https://lore.kernel.org/r/20251226-qcs615-spin-2-v5-0-354d86460ccb@oss.qualcomm.com Changes in v5: - Rebase on v6.19-rc2 - Make the reg list in A612 GPU's binding doc stricter (Krzysztof) - Link to v4: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-0-f5a00c5b663f@oss.qualcomm.com Changes in v4: - Rebased on top of next-20251204 tag - Added a new patch to simplify gpu dt schema (Krzysztof) - Added a new patch for GPU cooling support (Gaurav) - Updated the gpu/gmu register range in DT to be more accurate - Remove 290Mhz corner for GPU as that is not present in downstream - Link to v3: https://lore.kernel.org/r/20251122-qcs615-spin-2-v3-0-9f4d4c87f51d@oss.qualcomm.com Changes in v3: - Rebased on top of next-20251121 tag - Drop a612 driver support patch as it got picked up - Rename rgmu.yaml -> qcom,adreno-rgmu.yaml (Krzysztof) - Remove reg-names property for rgmu node (Krzysztof) - Use 'gmu' instead of 'rgmu' as node name (Krzysztof) - Describe cx_mem and cx_dgc register ranges (Krzysztof) - A new patch to retrieve gmu core reg resource by id - Link to v2: https://lore.kernel.org/r/20251107-qcs615-spin-2-v2-0-a2d7c4fbf6e6@oss.qualcomm.com Changes in v2: - Rebased on next-20251105 - Fix hwcg configuration (Dan) - Reuse a few gmu-wrapper routines (Konrad) - Split out rgmu dt schema (Krzysztof/Dmitry) - Fixes for GPU dt binding doc (Krzysztof) - Removed VDD_CX from rgmu dt node. Will post a separate series to address the gpucc changes (Konrad) - Fix the reg range size for adreno smmu node and reorder the properties (Konrad) - Link to v1: https://lore.kernel.org/r/20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com --- Akhil P Oommen (3): drm/msm/a6xx: Retrieve gmu core range by index dt-bindings: display/msm: gpu: Simplify conditional schema logic dt-bindings: display/msm: gpu: Document A612 GPU Gaurav Kohli (1): arm64: dts: qcom: talos: Add GPU cooling Jie Zhang (3): dt-bindings: display/msm/rgmu: Document A612 RGMU arm64: dts: qcom: talos: Add gpu and rgmu nodes arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Qingqing Zhou (1): arm64: dts: qcom: talos: add the GPU SMMU node .../devicetree/bindings/display/msm/gpu.yaml | 89 +++++++++--- .../bindings/display/msm/qcom,adreno-rgmu.yaml | 126 +++++++++++++++++ MAINTAINERS | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++ arch/arm64/boot/dts/qcom/talos.dtsi | 149 +++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 +- 6 files changed, 357 insertions(+), 30 deletions(-) --- base-commit: 2408853dde584f01950a0f976b743739cce30eca change-id: 20251015-qcs615-spin-2-ed45b0deb998 Best regards, -- Akhil P Oommen