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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-89075557adesm4736926d6.40.2026.01.05.11.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jan 2026 11:14:10 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vcq1q-00000001Cir-1EgS; Mon, 05 Jan 2026 15:14:10 -0400 Date: Mon, 5 Jan 2026 15:14:10 -0400 From: Jason Gunthorpe To: Dmytro Maluka Cc: David Woodhouse , Lu Baolu , iommu@lists.linux.dev, Joerg Roedel , Will Deacon , Robin Murphy , linux-kernel@vger.kernel.org, "Vineeth Pillai (Google)" , Aashish Sharma , Grzegorz Jaszczyk , Chuanxiao Dong , Kevin Tian Subject: Re: [PATCH v2 0/5] iommu/vt-d: Ensure memory ordering in context & root entry updates Message-ID: <20260105191410.GJ125261@ziepe.ca> References: <20251227175728.4358-1-dmaluka@chromium.org> <20260105181200.GH125261@ziepe.ca> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Jan 05, 2026 at 07:54:53PM +0100, Dmytro Maluka wrote: > > Like AMD and ARM build the new PASID entry on the stack and then it > > should be copied to the DMA'able memory in a way that is consistent > > with the HW's atomicity granual, paying attention not to 'tear' it. > > As I understand, the "consistent with the HW's atomicity granual, paying > attention not to 'tear' it" part is already fulfilled for PASID entries > (and with this series, for context entries as well): > > static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits) > { > u64 old; > > old = READ_ONCE(*ptr); > WRITE_ONCE(*ptr, (old & ~mask) | bits); > } > > I've been assuming it's ok to manipulate other bits in place as long as > we take care to only do that while the present bit it cleared (i.e. > while the entry is ignored by hardware)? If these are only done while non-present then the only issue is missing a barrier before setting present, that should be a one line patch, no? > So IIUC the only problem with this approach is the redundancy: we do > this READ_ONCE+WRITE_ONCE for each invididual field in a PASID entry. You don't need READ_ONCE if there isn't another thread concurrently writing, and WRITE_ONCE is pointless if the HW is promising not to read it due to non-present. > So while I agree it would be more more natural to build whole entries, > and the existing way looks strange and not the most efficient, I'm > wondering if it is causing any actual correctness issues (apart from > those addressed by this series). It prevents doing the replace operation, which is a correctness issue for VMs. Jason