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[2a02:3100:a8ad:5500:1e86:bff:fe2f:57b7]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-b842a233ef3sm26240566b.1.2026.01.05.12.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jan 2026 12:47:30 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, jian.hu@amlogic.com, jbrunet@baylibre.com, Martin Blumenstingl Subject: [PATCH v1 0/3] clk: meson: small fixes for HDMI PLL OD Date: Mon, 5 Jan 2026 21:47:07 +0100 Message-ID: <20260105204710.447779-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Jerome, this series contains two fixes for preventing HDMI PLL OD /8 on GXL/GXM and G12A/G12B/SM1, like the downstream driver does. See: - downstream GXBB code: [0] - downstream GXL/GXM code: [1] - downstream G12A/G12B/SM1 code: [2] I have verified this on GXL (Le Potato) by setting HDMI PLL OD1 to 0x3 (which should result in divide-by-8). The resulting frequency reported by meson-clk-msr is double (meaning: only divide-by-4) compared to what CCF sees. These are not critical for now since the CCF code-path for the HDMI PLL is read-only (as drm/meson directly programs the registers). Additionally there's a cosmetic fix to use the HHI_HDMI_PLL_CNTL3 macro instead of calculating HHI_HDMI_PLL_CNTL + 8. [0] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c#L505-L627 [1] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c#L501-L553 [2] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c#L671-L721 Martin Blumenstingl (3): clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs clk: meson: g12a: Limit the HDMI PLL OD to /4 clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro drivers/clk/meson/g12a.c | 13 ++++++++++--- drivers/clk/meson/gxbb.c | 19 +++++++++++++------ 2 files changed, 23 insertions(+), 9 deletions(-) -- 2.52.0