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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8c37f4ccdf8sm198944485a.23.2026.01.06.08.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jan 2026 08:45:19 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vdABK-00000001cAp-32IF; Tue, 06 Jan 2026 12:45:18 -0400 Date: Tue, 6 Jan 2026 12:45:18 -0400 From: Jason Gunthorpe To: Dmytro Maluka Cc: David Woodhouse , Lu Baolu , iommu@lists.linux.dev, Joerg Roedel , Will Deacon , Robin Murphy , linux-kernel@vger.kernel.org, "Vineeth Pillai (Google)" , Aashish Sharma , Grzegorz Jaszczyk , Chuanxiao Dong , Kevin Tian Subject: Re: [PATCH v2 0/5] iommu/vt-d: Ensure memory ordering in context & root entry updates Message-ID: <20260106164518.GA340082@ziepe.ca> References: <20251227175728.4358-1-dmaluka@chromium.org> <20260105181200.GH125261@ziepe.ca> <20260105191410.GJ125261@ziepe.ca> <20260106001418.GK125261@ziepe.ca> <20260106142301.GS125261@ziepe.ca> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jan 06, 2026 at 04:50:11PM +0100, Dmytro Maluka wrote: > So we'd better make sure that if it happens before the barrier (i.e. > when the device is not supposed to do DMA), the compiler (and thus > the CPU) doesn't set the present bit, so it stays non-present, so > the IOMMU will block this unexpected/malicious DMA? It is true that any write to the dword containing the present bit (only!) should probably use WRITE_ONCE. Jason