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Wed, 07 Jan 2026 11:45:45 -0800 (PST) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.41.122]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b842a233fb3sm591201066b.12.2026.01.07.11.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jan 2026 11:45:45 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , Srinivas Kandagatla , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/2] dt-bindings: nvmem: add STM32 TAMP NVRAM Date: Wed, 7 Jan 2026 20:45:32 +0100 Message-ID: <20260107194541.1843999-1-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add devicetree bindings for TAMP backup registers. These 32-bit registers are retained in all low-power modes and in VBAT mode. As a result, they can also be used to store sensitive data because their content is protected by a tamper detection circuit. Signed-off-by: Dario Binacchi --- .../bindings/nvmem/st,stm32-tamp-nvram.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.yaml diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.yaml b/Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.yaml new file mode 100644 index 000000000000..e03469fbe436 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/st,stm32-tamp-nvram.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/st,stm32-tamp-nvram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 TAMP's NVRAM + +description: | + The TAMP peripheral integrates, amongst others, Non Volatile RAM + (NVRAM) with 32/128 32-bit backup registers which can be used by + software to store information or communicate with a boot loader. + +maintainers: + - Dario Binacchi + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + enum: + - st,stm32mp15-tamp-nvram + - st,stm32mp25-tamp-nvram + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + nvram: nvram@46010100 { + compatible = "st,stm32mp25-tamp-nvram"; + reg = <0x46010100 0x200>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + fwu_info: tamp-bkp@c0 { + reg = <0xc0 0x4>; + }; + + boot_mode: tamp-bkp@180 { + reg = <0x180 0x4>; + }; + }; + }; +... -- 2.43.0 base-commit: f0b9d8eb98dfee8d00419aa07543bdc2c1a44fb1 branch: stm32-tamp-nvram