From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa1.hc555-34.eu.iphmx.com (esa1.hc555-34.eu.iphmx.com [23.90.104.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6B3C288515 for ; Thu, 8 Jan 2026 20:37:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=23.90.104.144 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767904648; cv=none; b=E3eV4ojHS9NYgUc+zjZqwZCh2Z9Nqgx85aqygtEVTgMvgVhK28c0tAiZ/VCZJBD1HBuGAI0qqK2fNB9zGoXnm7nQvHFEt6FFVwvJJXs3S6LEKuRabAnKbsvFJ2QAtoQ/53uB2nz/5Kn+VtGpZXcOipBRtjXxMtjackHrY5MAwrc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767904648; c=relaxed/simple; bh=fRiVey58MNMLYSH6+LLvPN7GGIPhKw56ttadILAx7Vw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bbzX0ejAXi3IxNKi1kH3T0PireUPZ/1gnWc/12ElAuWs6sEa7+p9qZLAw9XL6qR2sr1sVx6tyjNtlIqXeVvnh8XGI/oYRpEDPlbWnPAiXu6VFOXmFnq7ZhOdCAwov19/Fn4aiwesgXDEos27cgwWHEtR70jT2/+p9t+VAuxUs9A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mobileye.com; spf=pass smtp.mailfrom=mobileye.com; dkim=fail (0-bit key) header.d=mobileye.com header.i=@mobileye.com header.b=cTIMpbIJ reason="key not found in DNS"; arc=none smtp.client-ip=23.90.104.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mobileye.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mobileye.com Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mobileye.com header.i=@mobileye.com header.b="cTIMpbIJ" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mobileye.com; i=@mobileye.com; q=dns/txt; s=MoEyIP; t=1767904645; x=1799440645; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fRiVey58MNMLYSH6+LLvPN7GGIPhKw56ttadILAx7Vw=; b=cTIMpbIJ4evKck9fufTuQkHCuI/krt4ZvufYMJrrLFR1KwTHlTDEujDV 38KnlQzYiJrSf9IlnwAnMVBgFgoa4TJjsdsAUXi8NR2jHJknamLgtoeGL 7T2cV+z9iKBQ5ZKz6kNZBq5m6LgGj7qVs/DeBasPK9LDj0bjr0YiUt8Y7 Zi5anyKqbDUiCLkBGZ3UXyib5o7/Rgs37OoBWFP5sT7ArLaeLpFKyJwTH ndySMbvk4MfD9WkFiO3mRW0C41RbkqAG0q0eJEuEgzgbdFHB1JthLUNIp IAPqUeyLfqeDaC2LtzTUClOrnfZpmFD9dLCjj0HAn4JA+MVNTIL9nqhFr g==; X-CSE-ConnectionGUID: nVVN0+MSTTS79SJOXkzURg== X-CSE-MsgGUID: t63HUdzmQKyNEljzOlTPsw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from unknown (HELO ces02_data.me-corp.lan) ([146.255.191.134]) by esa1.hc555-34.eu.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2026 22:36:15 +0200 X-CSE-ConnectionGUID: K4tsZRD2SIihZSmfzeW8rw== X-CSE-MsgGUID: l/x33mfcQu6dRd9OsH3eXQ== Received: from unknown (HELO epgd034.me-corp.lan) ([10.154.54.2]) by ces02_data.me-corp.lan with SMTP; 08 Jan 2026 22:37:57 +0200 Received: by epgd034.me-corp.lan (sSMTP sendmail emulation); Thu, 08 Jan 2026 22:36:14 +0200 From: Pnina Feder To: akpm@linux-foundation.org Cc: pmladek@suse.com, bhe@redhat.com, linux-kernel@vger.kernel.org, lkp@intel.com, mgorman@suse.de, mingo@redhat.com, peterz@infradead.org, pnina.feder@mobileye.com, rostedt@goodmis.org, senozhatsky@chromium.org, tglx@linutronix.de, vkondra@mobileye.com Subject: [PATCH v5] panic: add panic_force_cpu= parameter to redirect panic to a specific CPU Date: Thu, 8 Jan 2026 22:36:12 +0200 Message-ID: <20260108203612.955769-1-pnina.feder@mobileye.com> In-Reply-To: <20260105081808.1771473-1-pnina.feder@mobileye.com> References: <20260105081808.1771473-1-pnina.feder@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Some platforms require panic handling to execute on a specific CPU for crash dump to work reliably. This can be due to firmware limitations, interrupt routing constraints, or platform-specific requirements where only a single CPU is able to safely enter the crash kernel. Add the panic_force_cpu= kernel command-line parameter to redirect panic execution to a designated CPU. When the parameter is provided, the CPU that initially triggers panic forwards the panic context to the target CPU via IPI, which then proceeds with the normal panic and kexec flow. The IPI delivery is implemented as a weak function (panic_smp_redirect_cpu) so architectures with NMI support can override it for more reliable delivery. If the specified CPU is invalid, offline, or a panic is already in progress on another CPU, the redirection is skipped and panic continues on the current CPU. Changes since v4: - Make IPI delivery an overridable weak function (panic_smp_redirect_cpu) so architectures can use NMI where available - Add declaration on include/linux/smp.h alongside other panic SMP functions - Add warning to documentation about reduced reliability - Address review comments from Andrew Morton (remove unnecessary cast, add missing kernel-doc parameters) Signed-off-by: Pnina Feder --- .../admin-guide/kernel-parameters.txt | 15 +++ include/linux/smp.h | 1 + kernel/panic.c | 122 ++++++++++++++++++ 3 files changed, 138 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index a8d0afde7f85..6d6f2880302f 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4753,6 +4753,21 @@ Kernel parameters panic_on_warn=1 panic() instead of WARN(). Useful to cause kdump on a WARN(). + panic_force_cpu= + [KNL,SMP] Force panic handling to execute on a specific CPU. + Format: + Some platforms require panic handling to occur on a + specific CPU for the crash kernel to function correctly. + This can be due to firmware limitations, interrupt routing + constraints, or platform-specific requirements where only + a particular CPU can safely enter the crash kernel. + When set, panic() will redirect execution to the specified + CPU before proceeding with the normal panic and kexec flow. + If the target CPU is offline or unavailable, panic proceeds + on the current CPU. + This option should only be used for systems with the above + constraints as it might cause the panic operation to be less reliable. + panic_print= Bitmask for printing system info when panic happens. User can chose combination of the following bits: bit 0: print all tasks info diff --git a/include/linux/smp.h b/include/linux/smp.h index 91d0ecf3b8d3..1ebd88026119 100644 --- a/include/linux/smp.h +++ b/include/linux/smp.h @@ -62,6 +62,7 @@ int smp_call_function_single_async(int cpu, call_single_data_t *csd); void __noreturn panic_smp_self_stop(void); void __noreturn nmi_panic_self_stop(struct pt_regs *regs); void crash_smp_send_stop(void); +int panic_smp_redirect_cpu(int target_cpu, void *msg); /* * Call a function on all processors diff --git a/kernel/panic.c b/kernel/panic.c index 0d52210a9e2b..f03eb60ae8ac 100644 --- a/kernel/panic.c +++ b/kernel/panic.c @@ -300,6 +300,121 @@ void __weak crash_smp_send_stop(void) atomic_t panic_cpu = ATOMIC_INIT(PANIC_CPU_INVALID); +#if defined(CONFIG_SMP) && defined(CONFIG_CRASH_DUMP) +/* CPU to redirect panic to, or -1 if disabled */ +static int panic_force_cpu = -1; + +static int __init panic_force_cpu_setup(char *str) +{ + int cpu; + + if (!str) + return -EINVAL; + + if (kstrtoint(str, 0, &cpu) || cpu < 0) { + pr_warn("panic_force_cpu: invalid value '%s'\n", str); + return -EINVAL; + } + + panic_force_cpu = cpu; + return 0; +} +early_param("panic_force_cpu", panic_force_cpu_setup); + +static void do_panic_on_target_cpu(void *info) +{ + panic("%s", info); +} + +/** + * panic_smp_redirect_cpu - Redirect panic to target CPU + * @target_cpu: CPU that should handle the panic + * @msg: formatted panic message + * + * Default implementation uses IPI. Architectures with NMI support + * can override this for more reliable delivery. + * + * Return: 0 on success, negative errno on failure + */ +int __weak panic_smp_redirect_cpu(int target_cpu, void *msg) +{ + static call_single_data_t panic_csd; + + panic_csd.func = do_panic_on_target_cpu; + panic_csd.info = msg; + + return smp_call_function_single_async(target_cpu, &panic_csd); +} + +/** + * panic_force_target_cpu - Redirect panic to a specific CPU for crash kernel + * @buf: buffer to format the panic message into + * @buf_size: size of the buffer + * @fmt: panic message format string + * @args: arguments for format string + * + * Some platforms require panic handling to occur on a specific CPU + * for the crash kernel to function correctly. This function redirects + * panic handling to the CPU specified via the panic_redirect_cpu= boot parameter. + * + * Returns true if panic should proceed on current CPU. + * Returns false (never returns) if panic was redirected. + */ +__printf(3, 0) +static bool panic_force_target_cpu(char *buf, int buf_size, const char *fmt, va_list args) +{ + int cpu = raw_smp_processor_id(); + int target_cpu = panic_force_cpu; + + /* Feature not enabled via boot parameter */ + if (target_cpu < 0) + return true; + + /* Already on target CPU - proceed normally */ + if (cpu == target_cpu) + return true; + + /* Target CPU is offline, can't redirect */ + if (!cpu_online(target_cpu)) + return true; + + /* Another panic already in progress */ + if (panic_in_progress()) + return true; + + vsnprintf(buf, buf_size, fmt, args); + + console_verbose(); + bust_spinlocks(1); + + pr_emerg("panic: Redirecting from CPU %d to CPU %d for crash kernel\n", + cpu, target_cpu); + + /* Dump original CPU's stack before redirecting */ + if (test_taint(TAINT_DIE) || oops_in_progress > 1) { + panic_this_cpu_backtrace_printed = true; + } else if (IS_ENABLED(CONFIG_DEBUG_BUGVERBOSE)) { + dump_stack(); + panic_this_cpu_backtrace_printed = true; + } + + printk_legacy_allow_panic_sync(); + console_flush_on_panic(CONSOLE_FLUSH_PENDING); + + if (panic_smp_redirect_cpu(target_cpu, buf) != 0) + return true; + + /* IPI/NMI sent, this CPU should stop */ + return false; +} +#else +__printf(3, 0) +static inline bool panic_force_target_cpu(char *buf, int buf_size, const char *fmt, va_list args) +{ + return true; +} +#endif /* CONFIG_SMP && CONFIG_CRASH_DUMP */ + bool panic_try_start(void) { int old_cpu, this_cpu; @@ -451,6 +566,13 @@ void vpanic(const char *fmt, va_list args) local_irq_disable(); preempt_disable_notrace(); + /* + * Redirect panic to target CPU if configured via panic_force_cpu=. + * Returns false and never returns if panic was redirected. + */ + if (!panic_force_target_cpu(buf, sizeof(buf), fmt, args)) + panic_smp_self_stop(); + /* * It's possible to come here directly from a panic-assertion and * not have preempt disabled. Some functions called from here want -- 2.43.0