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From: Jonathan Cameron <jic23@kernel.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: SeungJu Cheon <suunj1331@gmail.com>,
	antoniu.miclaus@analog.com, lars@metafoo.de,
	Michael.Hennerich@analog.com, andriy.shevchenko@intel.com,
	dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org,
	linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] iio:frequency:adf4377: Fix duplicated soft reset mask
Date: Sun, 11 Jan 2026 12:09:25 +0000	[thread overview]
Message-ID: <20260111120857.5087e396@jic23-huawei> (raw)
In-Reply-To: <CAHp75VdOX_h1Ksm4MbYyipiSpGrTp84GTkUAO9L_0o3auR3Xkg@mail.gmail.com>

On Wed, 31 Dec 2025 13:19:46 +0200
Andy Shevchenko <andy.shevchenko@gmail.com> wrote:

> On Tue, Dec 30, 2025 at 3:21 PM SeungJu Cheon <suunj1331@gmail.com> wrote:
> >
> > The regmap_read_poll_timeout() uses ADF4377_0000_SOFT_RESET_R_MSK
> > twice instead of checking both SOFT_RESET_MSK (bit 0) and
> > SOFT_RESET_R_MSK (bit 7). This causes incomplete reset status check.  
> 
> an incomplete
> 
> > Fix by using both masks as done in regmap_update_bits() above.  
> 
> ...
> 
> 
> May I ask how you tested this? Logically from the code it sounds
> correct, but I haven't read the datasheet yet, so I can't tell if this
> is the expected value to read or not.
> 
> 
> >         return regmap_read_poll_timeout(st->regmap, 0x0, read_val,
> > -                                       !(read_val & (ADF4377_0000_SOFT_RESET_R_MSK |
> > +                                       !(read_val & (ADF4377_0000_SOFT_RESET_MSK |
> >                                         ADF4377_0000_SOFT_RESET_R_MSK)), 200, 200 * 100);  
> 
> Okay, I opened the datasheet, and the below is what I read there. The
> code first sets the SOFT_RESET_R and SOFT_RESET bits to "1", and waits
> for them to be cleared. But the Table 43 does not mention that
> SOFT_RESET_R is auto cleaned, and actually I don't see with a brief
> look what the "repeat of" term means.
> 
> And for normal operation they needs to be 0ed as per:
>   "SOFT_RESET, SOFT_RESET_R, RST_SYS, and ADC_ST_CNV are the only
> remaining RW bit fields not mentioned yet, and must also be set to
> their POR state (see Table 34)."
> 
> With that said, I would wait for AD people to clarify the programming
> workflow here.
> 

Small kernel development process thing as well. Please don't send a v2 in reply to a v1.
It can become very confusing if we end up with a larger number of versions.
Much better to just post a new thread for each version, and include
a link back to the lore archive of the previous version in your cover letter.

Also from a practical point of view, it ends up pages up in people's inboxes and
so is is less likely to get reviewed!

Thanks

Jonathan

  reply	other threads:[~2026-01-11 12:09 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-30 12:36 [PATCH] " SeungJu Cheon
2025-12-30 12:57 ` Andy Shevchenko
2025-12-30 13:21 ` [PATCH v2] " SeungJu Cheon
2025-12-31 11:19   ` Andy Shevchenko
2026-01-11 12:09     ` Jonathan Cameron [this message]
2026-01-23  9:44       ` Jonathan Cameron
2026-01-23 10:08         ` Miclaus, Antoniu
2026-01-23 11:06           ` andriy.shevchenko
2026-01-23 11:56 SeungJu Cheon
2026-01-23 14:35 ` Andy Shevchenko

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