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Wed, 14 Jan 2026 22:52:03 -0800 (PST) From: Guodong Xu Subject: [PATCH v5 0/7] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Date: Thu, 15 Jan 2026 14:51:39 +0800 Message-Id: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAHuOaGkC/23QQWrDMBAF0KsErasympGNlVXvUbpQpFEjSuxUU k1KyN07SVqIi5d/xPuCf1aVS+aqtpuzKjznmqdRQve0UWHvx3fWOUpWCNgZNL3+IL3zNQcdmw7 RdRagN25wSsSxcMqnW9vrm+R9rm0q37fy2Vyv6z2z0aA9ROz64GJw+FJyDbX58hymg7pWzfjAE ZcchZNPlChESINf4fTHezAwLDkJ5+gc72wgH2mF2wduYMmt8GgdJvIEKf3//XIfpvDnl6zb7us o4azl/ZDbdjPyqenfcivi8gPXxYELlwEAAA== X-Change-ID: 20251216-k3-basic-dt-cd9540061989 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen , Thomas Gleixner , Thomas Gleixner Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Krzysztof Kozlowski , Heinrich Schuchardt , Conor Dooley X-Mailer: b4 0.14.3 This series introduces basic support for the SpacemiT K3 SoC and the K3 Pico-ITX evaluation board. In v5, patches 6-9 (dt-bindings) have been dropped as they were accepted by Conor and applied to riscv-dt-for-next. The series has been rebased on linux-next tag: next-20260114. The SpacemiT K3 is an SoC featuring 8 SpacemiT X100 RISC-V cores. The X100 is a 4-issue, out-of-order core compliant with the RVA23 profile, targeting high-performance scenarios. [1] The K3 Pico-ITX is an evaluation board built around the K3 SoC. >From an RVA23 profile compliance perspective, the X100 supports all mandatory extensions required by RVA23U64 and RVA23S64. Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Changes in v5: - Patch 1: Add Acked-by from Paul. - Patch 5: Add Reviewed-by from Yixun, add Acked-by from Conor. - Patch 6 (Patch 10 in v4): Update the copyright year to 2026. Update the commit message. Set M-mode maplic and mimsic status to "reserved". In maplic node, use riscv,delegation to match kernel binding. OpenSBI accepts both delegate and delgation, but the binding documents only riscv,delegation. - Patch 7 (Patch 11 in v4): Update the commit message subject line. Remove the unused aliases. Update the copyright year to 2026. - Link to v4: https://lore.kernel.org/r/20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com Changes in v4: - Patch 5: Adjust maintainers list in alphabetic order. Declare spacemit,k3-pico-itx as an enum, which could save future code change when adding new boards. - Patch 10: Fix missing blank space after comma in simsic compatible. Add m-mode imsic and aplic nodes, per suggestion received from Samuel Holland. Adjust node properties order in nodes simsic, saplic, mimsic, maplic to follow the DTS coding style. - Link to v3: https://lore.kernel.org/r/20260108-k3-basic-dt-v3-0-ed99eb4c3ad3@riscstar.com Other Changes in v3 include: - Patch 1: Acked-by: Krzysztof Kozlowski - Patch 4: Acked-by: Krzysztof Kozlowski - Dropped Patch 5 "dt-bindings: serial: 8250: add SpacemiT K3 UART compatible" as it has been applied to tty-next. - Link to v2: https://lore.kernel.org/r/20251222-k3-basic-dt-v2-0-3af3f3cd0f8a@riscstar.com Changes in v2: - Patch 1: Fixed alphanumeric sorting order of compatible strings (swapped x100 and x60) as per Krzysztof's feedback. Update commit message with more information about X100 featurs per Yixun's feedback. - Patch 4: Fixed the order to keep things alphabetically. - Patch 6: Use "one blank space" between name and email address. - Patch 7 ~ 11: New patches. Add description of RVA23 mandatory extensions into riscv binding YAML file. - Patch 12 (Patch 7 in v1): Removed aliases node. Updated 'riscv,isa-extensions' with new extension strings available - Patch 13 (Patch 8 in v1): Updated the memory address to the hardware truth. Added aliases node in board dts. - Patch 1,2,3,5: Add Reviewed-by and Acked-by collected. Link to v1: https://lore.kernel.org/r/20251216-k3-basic-dt-v1-0-a0d256c9dc92@riscstar.com Signed-off-by: Guodong Xu --- Guodong Xu (7): dt-bindings: riscv: add SpacemiT X100 CPU compatible dt-bindings: timer: add SpacemiT K3 CLINT dt-bindings: interrupt-controller: add SpacemiT K3 APLIC dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings riscv: dts: spacemit: add initial support for K3 SoC riscv: dts: spacemit: add K3 Pico-ITX board support .../bindings/interrupt-controller/riscv,aplic.yaml | 1 + .../interrupt-controller/riscv,imsics.yaml | 1 + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/spacemit.yaml | 5 + .../devicetree/bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/spacemit/Makefile | 1 + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 + arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++ 8 files changed, 629 insertions(+) --- base-commit: 78ffa9bb137071c00eec2d4afc247ef92d5c0b90 change-id: 20251216-k3-basic-dt-cd9540061989 Best regards, -- Guodong Xu