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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-434af653596sm6626191f8f.14.2026.01.15.07.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 07:10:22 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , devicetree , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stafford Horne Subject: [PATCH v6 0/6] OpenRISC de0 nano single and multicore boards Date: Thu, 15 Jan 2026 15:09:56 +0000 Message-ID: <20260115151014.3956805-1-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since v5: - Adjust dt-binding patch based on suggestions from Geert and Krzysztof. - Add reviewed-by's on the dt-binding patch. Since v4: - Rebased the series on linux-next to allow patches to be incremental. - Rewrote the dt-bindings patch as an incremental patch, Due to this I dropped reviewed-by's. - Added acked-by to the IPI fix patch. Since v3: - Switch order of gpio-mmio driver and bindings patches to patch binding first before driver. Suggested by Krzysztof. - Removed example form binding suggested by Krzysztof. - Added Reviewed-by's from Geert and Linus W. Since v2: - Fixup (replace) gpio-mmio patch to update driver compatible list and just add opencores,gpio to mmio-gpio bindings. Discussed with Geert and Linus W because the 8-bit opencores,gpio is not the same as the 32-bit broadcom chip. [1]. - Update new device trees to use proper ordering, remove debug options, remove unneeded "status" properties. Suggested by Geert. Since v1: - Use proper schema in gpio-mmio suggsted by Conor Dooley - Remove 0 clock-frequency definitions in dtsi file The patches add support for OpenRISC systems running on the De0 Nano FPGA development board. We have two SoCs which are available here: - https://github.com/olofk/de0_nano - Single core - https://github.com/stffrdhrn/de0_nano-multicore - Multicore As I work on tutorials [2] to help other get started with OpenRISC I would like to have these defconfig and devicetree definitions in the upstream kernel to avoid losing them. When I was working on resurrecting these old setup's I found a major bug in OpenRISC SMP which is fixed in this series as well. [1] https://lore.kernel.org/lkml/20251217080843.70621-1-shorne@gmail.com/ [2] https://openrisc.io/tutorials/ Stafford Horne (6): dt-bindings: gpio-mmio: Correct opencores GPIO gpio: mmio: Add compatible for opencores GPIO openrisc: dts: Add de0 nano config and devicetree openrisc: Fix IPIs on simple multicore systems openrisc: dts: Split simple smp dts to dts and dtsi openrisc: dts: Add de0 nano multicore config and devicetree .../devicetree/bindings/gpio/gpio-mmio.yaml | 16 ++-- arch/openrisc/boot/dts/de0-nano-common.dtsi | 42 +++++++++ arch/openrisc/boot/dts/de0-nano-multicore.dts | 25 +++++ arch/openrisc/boot/dts/de0-nano.dts | 54 +++++++++++ arch/openrisc/boot/dts/simple-smp.dts | 25 +++++ .../dts/{simple_smp.dts => simple-smp.dtsi} | 11 +-- arch/openrisc/configs/de0_nano_defconfig | 79 ++++++++++++++++ .../configs/de0_nano_multicore_defconfig | 92 +++++++++++++++++++ arch/openrisc/configs/simple_smp_defconfig | 2 +- arch/openrisc/include/asm/smp.h | 3 +- arch/openrisc/kernel/smp.c | 22 ++++- drivers/gpio/gpio-mmio.c | 1 + drivers/irqchip/irq-ompic.c | 15 ++- drivers/irqchip/irq-or1k-pic.c | 27 +++++- 14 files changed, 390 insertions(+), 24 deletions(-) create mode 100644 arch/openrisc/boot/dts/de0-nano-common.dtsi create mode 100644 arch/openrisc/boot/dts/de0-nano-multicore.dts create mode 100644 arch/openrisc/boot/dts/de0-nano.dts create mode 100644 arch/openrisc/boot/dts/simple-smp.dts rename arch/openrisc/boot/dts/{simple_smp.dts => simple-smp.dtsi} (90%) create mode 100644 arch/openrisc/configs/de0_nano_defconfig create mode 100644 arch/openrisc/configs/de0_nano_multicore_defconfig -- 2.51.0