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From: Ryan Roberts <ryan.roberts@arm.com>
To: Will Deacon <will@kernel.org>, Ard Biesheuvel <ardb@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Oliver Upton <oliver.upton@linux.dev>,
	Marc Zyngier <maz@kernel.org>, Dev Jain <dev.jain@arm.com>,
	Linu Cherian <Linu.Cherian@arm.com>,
	Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Linu Cherian <linu.cherian@arm.com>
Subject: [PATCH v2 13/13] arm64: mm: Provide level hint for flush_tlb_page()
Date: Mon, 19 Jan 2026 17:22:00 +0000	[thread overview]
Message-ID: <20260119172202.1681510-14-ryan.roberts@arm.com> (raw)
In-Reply-To: <20260119172202.1681510-1-ryan.roberts@arm.com>

Previously tlb invalidations issued by __flush_tlb_page() did not
contain a level hint. But the function is clearly only ever targeting
level 3 tlb entries and its documentation agrees:

  | this operation only invalidates a single, last-level page-table
  | entry and therefore does not affect any walk-caches

However, it turns out that the function was actually being used to
invalidate a level 2 mapping via flush_tlb_fix_spurious_fault_pmd(). The
bug was benign because the level hint was not set so the HW would still
invalidate the PMD mapping, and also because the TLBF_NONOTIFY flag was
set, the bounds of the mapping were never used for anything else.

Now that we have the new and improved range-invalidation API, it is
trival to fix flush_tlb_fix_spurious_fault_pmd() to explicitly flush the
whole range (locally, without notification and last level only). So
let's do that, and then update __flush_tlb_page() to hint level 3.

Reviewed-by: Linu Cherian <linu.cherian@arm.com>
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
 arch/arm64/include/asm/pgtable.h  | 5 +++--
 arch/arm64/include/asm/tlbflush.h | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index b96a7ca465a1..61f57647361a 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -138,8 +138,9 @@ static inline void arch_leave_lazy_mmu_mode(void)
 #define flush_tlb_fix_spurious_fault(vma, address, ptep)	\
 	__flush_tlb_page(vma, address, TLBF_NOBROADCAST | TLBF_NONOTIFY)
 
-#define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp)	\
-	__flush_tlb_page(vma, address, TLBF_NOBROADCAST | TLBF_NONOTIFY)
+#define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp)			\
+	__flush_tlb_range(vma, address, address + PMD_SIZE, PMD_SIZE, 2,	\
+			  TLBF_NOBROADCAST | TLBF_NONOTIFY | TLBF_NOWALKCACHE)
 
 /*
  * ZERO_PAGE is a global shared page that is always zero: used
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 88f46760e2c2..550908631f97 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -592,7 +592,7 @@ static inline void __flush_tlb_page(struct vm_area_struct *vma,
 	unsigned long start = round_down(uaddr, PAGE_SIZE);
 	unsigned long end = start + PAGE_SIZE;
 
-	___flush_tlb_range(vma, start, end, PAGE_SIZE, TLBI_TTL_UNKNOWN,
+	___flush_tlb_range(vma, start, end, PAGE_SIZE, 3,
 			   TLBF_NOWALKCACHE | flags);
 }
 
-- 
2.43.0


      parent reply	other threads:[~2026-01-19 17:22 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-19 17:21 [PATCH v2 00/13] arm64: Refactor TLB invalidation API and implementation Ryan Roberts
2026-01-19 17:21 ` [PATCH v2 01/13] arm64: mm: Re-implement the __tlbi_level macro as a C function Ryan Roberts
2026-01-27 11:12   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 02/13] arm64: mm: Introduce a C wrapper for by-range TLB invalidation Ryan Roberts
2026-01-27 11:19   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 03/13] arm64: mm: Implicitly invalidate user ASID based on TLBI operation Ryan Roberts
2026-01-27 11:31   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 04/13] arm64: mm: Push __TLBI_VADDR() into __tlbi_level() Ryan Roberts
2026-01-27 11:37   ` Jonathan Cameron
2026-01-27 13:26     ` Ryan Roberts
2026-01-19 17:21 ` [PATCH v2 05/13] arm64: mm: Inline __TLBI_VADDR_RANGE() into __tlbi_range() Ryan Roberts
2026-01-27 11:46   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 06/13] arm64: mm: Re-implement the __flush_tlb_range_op macro in C Ryan Roberts
2026-01-27 12:06   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 07/13] arm64: mm: Simplify __TLBI_RANGE_NUM() macro Ryan Roberts
2026-01-27 12:09   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 08/13] arm64: mm: Simplify __flush_tlb_range_limit_excess() Ryan Roberts
2026-01-27 12:15   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 09/13] arm64: mm: Refactor flush_tlb_page() to use __tlbi_level_asid() Ryan Roberts
2026-01-27 12:25   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 10/13] arm64: mm: Refactor __flush_tlb_range() to take flags Ryan Roberts
2026-01-27 12:28   ` Jonathan Cameron
2026-01-19 17:21 ` [PATCH v2 11/13] arm64: mm: More flags for __flush_tlb_range() Ryan Roberts
2026-01-27 12:45   ` Jonathan Cameron
2026-01-27 13:50     ` Ryan Roberts
2026-01-27 14:11       ` Jonathan Cameron
2026-01-27 14:14         ` Jonathan Cameron
2026-01-27 14:47           ` Ryan Roberts
2026-01-19 17:21 ` [PATCH v2 12/13] arm64: mm: Wrap flush_tlb_page() around ___flush_tlb_range() Ryan Roberts
2026-01-27 12:59   ` Jonathan Cameron
2026-01-27 14:03     ` Ryan Roberts
2026-01-27 14:08       ` Jonathan Cameron
2026-01-19 17:22 ` Ryan Roberts [this message]

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