From: Anup Patel <anup.patel@oss.qualcomm.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atish.patra@linux.dev>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <pjw@kernel.org>, Alexandre Ghiti <alex@ghiti.fr>,
Shuah Khan <shuah@kernel.org>, Anup Patel <anup@brainfault.org>,
Andrew Jones <andrew.jones@oss.qualcomm.com>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Anup Patel <anup.patel@oss.qualcomm.com>
Subject: [PATCH 08/27] RISC-V: KVM: Factor-out VCPU config into separate sources
Date: Tue, 20 Jan 2026 13:29:54 +0530 [thread overview]
Message-ID: <20260120080013.2153519-9-anup.patel@oss.qualcomm.com> (raw)
In-Reply-To: <20260120080013.2153519-1-anup.patel@oss.qualcomm.com>
The VCPU config deals with hideleg, hedeleg, henvcfg, and hstateenX
CSR configuration for each VCPU. Factor-out VCPU config into separate
sources so that VCPU config can do things differently for guest HS-mode
and guest VS/VU-mode.
Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com>
---
arch/riscv/include/asm/kvm_host.h | 20 +----
arch/riscv/include/asm/kvm_vcpu_config.h | 25 ++++++
arch/riscv/kvm/Makefile | 1 +
arch/riscv/kvm/main.c | 4 +-
arch/riscv/kvm/vcpu.c | 79 ++++--------------
arch/riscv/kvm/vcpu_config.c | 101 +++++++++++++++++++++++
6 files changed, 144 insertions(+), 86 deletions(-)
create mode 100644 arch/riscv/include/asm/kvm_vcpu_config.h
create mode 100644 arch/riscv/kvm/vcpu_config.c
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index f3a41a1be678..11c3566318ae 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -18,6 +18,7 @@
#include <asm/ptrace.h>
#include <asm/kvm_tlb.h>
#include <asm/kvm_vmid.h>
+#include <asm/kvm_vcpu_config.h>
#include <asm/kvm_vcpu_fp.h>
#include <asm/kvm_vcpu_insn.h>
#include <asm/kvm_vcpu_sbi.h>
@@ -47,18 +48,6 @@
#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
-#define KVM_HEDELEG_DEFAULT (BIT(EXC_INST_MISALIGNED) | \
- BIT(EXC_INST_ILLEGAL) | \
- BIT(EXC_BREAKPOINT) | \
- BIT(EXC_SYSCALL) | \
- BIT(EXC_INST_PAGE_FAULT) | \
- BIT(EXC_LOAD_PAGE_FAULT) | \
- BIT(EXC_STORE_PAGE_FAULT))
-
-#define KVM_HIDELEG_DEFAULT (BIT(IRQ_VS_SOFT) | \
- BIT(IRQ_VS_TIMER) | \
- BIT(IRQ_VS_EXT))
-
#define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
KVM_DIRTY_LOG_INITIALLY_SET)
@@ -167,13 +156,6 @@ struct kvm_vcpu_csr {
unsigned long senvcfg;
};
-struct kvm_vcpu_config {
- u64 henvcfg;
- u64 hstateen0;
- unsigned long hedeleg;
- unsigned long hideleg;
-};
-
struct kvm_vcpu_smstateen_csr {
unsigned long sstateen0;
};
diff --git a/arch/riscv/include/asm/kvm_vcpu_config.h b/arch/riscv/include/asm/kvm_vcpu_config.h
new file mode 100644
index 000000000000..fcc15a0296b3
--- /dev/null
+++ b/arch/riscv/include/asm/kvm_vcpu_config.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2026 Qualcomm Technologies, Inc.
+ */
+
+#ifndef __KVM_VCPU_RISCV_CONFIG_H
+#define __KVM_VCPU_RISCV_CONFIG_H
+
+#include <linux/types.h>
+
+struct kvm_vcpu;
+
+struct kvm_vcpu_config {
+ u64 henvcfg;
+ u64 hstateen0;
+ unsigned long hedeleg;
+ unsigned long hideleg;
+};
+
+void kvm_riscv_vcpu_config_init(struct kvm_vcpu *vcpu);
+void kvm_riscv_vcpu_config_guest_debug(struct kvm_vcpu *vcpu);
+void kvm_riscv_vcpu_config_ran_once(struct kvm_vcpu *vcpu);
+void kvm_riscv_vcpu_config_load(struct kvm_vcpu *vcpu);
+
+#endif
diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile
index 07eab96189e7..296c2ba05089 100644
--- a/arch/riscv/kvm/Makefile
+++ b/arch/riscv/kvm/Makefile
@@ -21,6 +21,7 @@ kvm-y += mmu.o
kvm-y += nacl.o
kvm-y += tlb.o
kvm-y += vcpu.o
+kvm-y += vcpu_config.o
kvm-y += vcpu_exit.o
kvm-y += vcpu_fp.o
kvm-y += vcpu_insn.o
diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
index 45536af521f0..588a84783dff 100644
--- a/arch/riscv/kvm/main.c
+++ b/arch/riscv/kvm/main.c
@@ -41,8 +41,8 @@ int kvm_arch_enable_virtualization_cpu(void)
if (rc)
return rc;
- csr_write(CSR_HEDELEG, KVM_HEDELEG_DEFAULT);
- csr_write(CSR_HIDELEG, KVM_HIDELEG_DEFAULT);
+ csr_write(CSR_HEDELEG, 0);
+ csr_write(CSR_HIDELEG, 0);
/* VS should access only the time counter directly. Everything else should trap */
csr_write(CSR_HCOUNTEREN, 0x02);
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 494e0517ca4e..62599fc002e8 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -133,11 +133,12 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
/* Mark this VCPU never ran */
vcpu->arch.ran_atleast_once = false;
- vcpu->arch.cfg.hedeleg = KVM_HEDELEG_DEFAULT;
- vcpu->arch.cfg.hideleg = KVM_HIDELEG_DEFAULT;
vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO;
bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX);
+ /* Setup VCPU config */
+ kvm_riscv_vcpu_config_init(vcpu);
+
/* Setup ISA features available to VCPU */
kvm_riscv_vcpu_setup_isa(vcpu);
@@ -530,57 +531,25 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
struct kvm_guest_debug *dbg)
{
- if (dbg->control & KVM_GUESTDBG_ENABLE) {
+ if (dbg->control & KVM_GUESTDBG_ENABLE)
vcpu->guest_debug = dbg->control;
- vcpu->arch.cfg.hedeleg &= ~BIT(EXC_BREAKPOINT);
- } else {
+ else
vcpu->guest_debug = 0;
- vcpu->arch.cfg.hedeleg |= BIT(EXC_BREAKPOINT);
- }
-
+ kvm_riscv_vcpu_config_guest_debug(vcpu);
return 0;
}
-static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
-{
- const unsigned long *isa = vcpu->arch.isa;
- struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
-
- if (riscv_isa_extension_available(isa, SVPBMT))
- cfg->henvcfg |= ENVCFG_PBMTE;
-
- if (riscv_isa_extension_available(isa, SSTC))
- cfg->henvcfg |= ENVCFG_STCE;
-
- if (riscv_isa_extension_available(isa, ZICBOM))
- cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
-
- if (riscv_isa_extension_available(isa, ZICBOZ))
- cfg->henvcfg |= ENVCFG_CBZE;
-
- if (riscv_isa_extension_available(isa, SVADU) &&
- !riscv_isa_extension_available(isa, SVADE))
- cfg->henvcfg |= ENVCFG_ADUE;
-
- if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
- cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
- if (riscv_isa_extension_available(isa, SSAIA))
- cfg->hstateen0 |= SMSTATEEN0_AIA_IMSIC |
- SMSTATEEN0_AIA |
- SMSTATEEN0_AIA_ISEL;
- if (riscv_isa_extension_available(isa, SMSTATEEN))
- cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0;
- }
-
- if (vcpu->guest_debug)
- cfg->hedeleg &= ~BIT(EXC_BREAKPOINT);
-}
-
void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
{
void *nsh;
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
- struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
+
+ /*
+ * Load VCPU config CSRs before other CSRs because
+ * the read/write behaviour of certain CSRs change
+ * based on VCPU config CSRs.
+ */
+ kvm_riscv_vcpu_config_load(vcpu);
if (kvm_riscv_nacl_sync_csr_available()) {
nsh = nacl_shmem();
@@ -591,18 +560,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
nacl_csr_write(nsh, CSR_VSEPC, csr->vsepc);
nacl_csr_write(nsh, CSR_VSCAUSE, csr->vscause);
nacl_csr_write(nsh, CSR_VSTVAL, csr->vstval);
- nacl_csr_write(nsh, CSR_HEDELEG, cfg->hedeleg);
- nacl_csr_write(nsh, CSR_HIDELEG, cfg->hideleg);
nacl_csr_write(nsh, CSR_HVIP, csr->hvip);
nacl_csr_write(nsh, CSR_VSATP, csr->vsatp);
- nacl_csr_write(nsh, CSR_HENVCFG, cfg->henvcfg);
- if (IS_ENABLED(CONFIG_32BIT))
- nacl_csr_write(nsh, CSR_HENVCFGH, cfg->henvcfg >> 32);
- if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
- nacl_csr_write(nsh, CSR_HSTATEEN0, cfg->hstateen0);
- if (IS_ENABLED(CONFIG_32BIT))
- nacl_csr_write(nsh, CSR_HSTATEEN0H, cfg->hstateen0 >> 32);
- }
} else {
csr_write(CSR_VSSTATUS, csr->vsstatus);
csr_write(CSR_VSIE, csr->vsie);
@@ -611,18 +570,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
csr_write(CSR_VSEPC, csr->vsepc);
csr_write(CSR_VSCAUSE, csr->vscause);
csr_write(CSR_VSTVAL, csr->vstval);
- csr_write(CSR_HEDELEG, cfg->hedeleg);
- csr_write(CSR_HIDELEG, cfg->hideleg);
csr_write(CSR_HVIP, csr->hvip);
csr_write(CSR_VSATP, csr->vsatp);
- csr_write(CSR_HENVCFG, cfg->henvcfg);
- if (IS_ENABLED(CONFIG_32BIT))
- csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32);
- if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
- csr_write(CSR_HSTATEEN0, cfg->hstateen0);
- if (IS_ENABLED(CONFIG_32BIT))
- csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32);
- }
}
kvm_riscv_mmu_update_hgatp(vcpu);
@@ -871,7 +820,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
struct kvm_run *run = vcpu->run;
if (!vcpu->arch.ran_atleast_once)
- kvm_riscv_vcpu_setup_config(vcpu);
+ kvm_riscv_vcpu_config_ran_once(vcpu);
/* Mark this VCPU ran at least once */
vcpu->arch.ran_atleast_once = true;
diff --git a/arch/riscv/kvm/vcpu_config.c b/arch/riscv/kvm/vcpu_config.c
new file mode 100644
index 000000000000..eb7374402b07
--- /dev/null
+++ b/arch/riscv/kvm/vcpu_config.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2026 Qualcomm Technologies, Inc.
+ */
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_nacl.h>
+
+#define KVM_HEDELEG_DEFAULT (BIT(EXC_INST_MISALIGNED) | \
+ BIT(EXC_INST_ILLEGAL) | \
+ BIT(EXC_BREAKPOINT) | \
+ BIT(EXC_SYSCALL) | \
+ BIT(EXC_INST_PAGE_FAULT) | \
+ BIT(EXC_LOAD_PAGE_FAULT) | \
+ BIT(EXC_STORE_PAGE_FAULT))
+
+#define KVM_HIDELEG_DEFAULT (BIT(IRQ_VS_SOFT) | \
+ BIT(IRQ_VS_TIMER) | \
+ BIT(IRQ_VS_EXT))
+
+void kvm_riscv_vcpu_config_init(struct kvm_vcpu *vcpu)
+{
+ vcpu->arch.cfg.hedeleg = KVM_HEDELEG_DEFAULT;
+ vcpu->arch.cfg.hideleg = KVM_HIDELEG_DEFAULT;
+}
+
+void kvm_riscv_vcpu_config_guest_debug(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
+
+ if (vcpu->guest_debug)
+ cfg->hedeleg &= ~BIT(EXC_BREAKPOINT);
+ else
+ cfg->hedeleg |= BIT(EXC_BREAKPOINT);
+}
+
+void kvm_riscv_vcpu_config_ran_once(struct kvm_vcpu *vcpu)
+{
+ const unsigned long *isa = vcpu->arch.isa;
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
+
+ if (riscv_isa_extension_available(isa, SVPBMT))
+ cfg->henvcfg |= ENVCFG_PBMTE;
+
+ if (riscv_isa_extension_available(isa, SSTC))
+ cfg->henvcfg |= ENVCFG_STCE;
+
+ if (riscv_isa_extension_available(isa, ZICBOM))
+ cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
+
+ if (riscv_isa_extension_available(isa, ZICBOZ))
+ cfg->henvcfg |= ENVCFG_CBZE;
+
+ if (riscv_isa_extension_available(isa, SVADU) &&
+ !riscv_isa_extension_available(isa, SVADE))
+ cfg->henvcfg |= ENVCFG_ADUE;
+
+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
+ cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
+ if (riscv_isa_extension_available(isa, SSAIA))
+ cfg->hstateen0 |= SMSTATEEN0_AIA_IMSIC |
+ SMSTATEEN0_AIA |
+ SMSTATEEN0_AIA_ISEL;
+ if (riscv_isa_extension_available(isa, SMSTATEEN))
+ cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0;
+ }
+
+ if (vcpu->guest_debug)
+ cfg->hedeleg &= ~BIT(EXC_BREAKPOINT);
+}
+
+void kvm_riscv_vcpu_config_load(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
+ void *nsh;
+
+ if (kvm_riscv_nacl_sync_csr_available()) {
+ nsh = nacl_shmem();
+ nacl_csr_write(nsh, CSR_HEDELEG, cfg->hedeleg);
+ nacl_csr_write(nsh, CSR_HIDELEG, cfg->hideleg);
+ nacl_csr_write(nsh, CSR_HENVCFG, cfg->henvcfg);
+ if (IS_ENABLED(CONFIG_32BIT))
+ nacl_csr_write(nsh, CSR_HENVCFGH, cfg->henvcfg >> 32);
+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
+ nacl_csr_write(nsh, CSR_HSTATEEN0, cfg->hstateen0);
+ if (IS_ENABLED(CONFIG_32BIT))
+ nacl_csr_write(nsh, CSR_HSTATEEN0H, cfg->hstateen0 >> 32);
+ }
+ } else {
+ csr_write(CSR_HEDELEG, cfg->hedeleg);
+ csr_write(CSR_HIDELEG, cfg->hideleg);
+ csr_write(CSR_HENVCFG, cfg->henvcfg);
+ if (IS_ENABLED(CONFIG_32BIT))
+ csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32);
+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
+ csr_write(CSR_HSTATEEN0, cfg->hstateen0);
+ if (IS_ENABLED(CONFIG_32BIT))
+ csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32);
+ }
+ }
+}
--
2.43.0
next prev parent reply other threads:[~2026-01-20 8:00 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-20 7:59 [PATCH 00/27] Nested virtualization for KVM RISC-V Anup Patel
2026-01-20 7:59 ` [PATCH 01/27] RISC-V: KVM: Fix error code returned for Smstateen ONE_REG Anup Patel
2026-03-06 7:04 ` Anup Patel
2026-01-20 7:59 ` [PATCH 02/27] RISC-V: KVM: Fix error code returned for Ssaia ONE_REG Anup Patel
2026-03-06 7:04 ` Anup Patel
2026-01-20 7:59 ` [PATCH 03/27] RISC-V: KVM: Check host Ssaia extension when creating AIA irqchip Anup Patel
2026-03-06 7:04 ` Anup Patel
2026-01-20 7:59 ` [PATCH 04/27] RISC-V: KVM: Introduce common kvm_riscv_isa_check_host() Anup Patel
2026-03-13 14:22 ` Radim Krčmář
2026-01-20 7:59 ` [PATCH 05/27] RISC-V: KVM: Factor-out ISA checks into separate sources Anup Patel
2026-03-13 14:14 ` Radim Krčmář
2026-04-03 12:34 ` Anup Patel
2026-01-20 7:59 ` [PATCH 06/27] RISC-V: KVM: Move timer state defines closer to struct in UAPI header Anup Patel
2026-01-20 7:59 ` [PATCH 07/27] RISC-V: KVM: Add hideleg to struct kvm_vcpu_config Anup Patel
2026-03-13 13:49 ` Radim Krčmář
2026-01-20 7:59 ` Anup Patel [this message]
2026-03-13 13:46 ` [PATCH 08/27] RISC-V: KVM: Factor-out VCPU config into separate sources Radim Krčmář
2026-01-20 7:59 ` [PATCH 09/27] RISC-V: KVM: Don't check hstateen0 when updating sstateen0 CSR Anup Patel
2026-03-13 13:27 ` Radim Krčmář
2026-01-20 7:59 ` [PATCH 10/27] RISC-V: KVM: Initial skeletal nested virtualization support Anup Patel
2026-01-20 7:59 ` [PATCH 11/27] RISC-V: KVM: Use half VMID space for nested guest Anup Patel
2026-01-20 7:59 ` [PATCH 12/27] RISC-V: KVM: Extend kvm_riscv_mmu_update_hgatp() for nested virtualization Anup Patel
2026-01-20 7:59 ` [PATCH 13/27] RISC-V: KVM: Extend kvm_riscv_vcpu_config_load() " Anup Patel
2026-01-20 8:00 ` [PATCH 14/27] RISC-V: KVM: Extend kvm_riscv_vcpu_update_timedelta() for nested virt Anup Patel
2026-01-20 8:00 ` [PATCH 15/27] RISC-V: KVM: Extend trap redirection for nested virtualization Anup Patel
2026-01-20 8:00 ` [PATCH 16/27] RISC-V: KVM: Check and inject nested virtual interrupts Anup Patel
2026-01-20 8:00 ` [PATCH 17/27] RISC-V: KVM: Extend kvm_riscv_isa_check_host() for nested virt Anup Patel
2026-01-20 8:00 ` [PATCH 18/27] RISC-V: KVM: Trap-n-emulate SRET for Guest HS-mode Anup Patel
2026-01-20 8:00 ` [PATCH 19/27] RISC-V: KVM: Redirect nested supervisor ecall and breakpoint traps Anup Patel
2026-01-20 8:00 ` [PATCH 20/27] RISC-V: KVM: Redirect nested WFI and WRS traps Anup Patel
2026-01-20 8:00 ` [PATCH 21/27] RISC-V: KVM: Implement remote HFENCE SBI calls for guest Anup Patel
2026-01-20 8:00 ` [PATCH 22/27] RISC-V: KVM: Add CSR emulation for nested virtualization Anup Patel
2026-01-20 8:00 ` [PATCH 23/27] RISC-V: KVM: Add HFENCE " Anup Patel
2026-01-20 8:00 ` [PATCH 24/27] RISC-V: KVM: Add ONE_REG interface for nested virtualization state Anup Patel
2026-01-20 8:00 ` [PATCH 25/27] RISC-V: KVM: selftests: Add nested virt state to get-reg-list test Anup Patel
2026-01-20 8:00 ` [PATCH 26/27] RISC-V: KVM: Add ONE_REG interface for nested virtualization CSRs Anup Patel
2026-01-20 8:00 ` [PATCH 27/27] RISC-V: KVM: selftests: Add nested virt CSRs to get-reg-list test Anup Patel
2026-04-03 12:36 ` [PATCH 00/27] Nested virtualization for KVM RISC-V Anup Patel
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