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([223.74.152.156]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7190ab96fsm128243035ad.13.2026.01.20.06.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 06:44:45 -0800 (PST) From: Nadi Ke To: sboyd@kernel.org, mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, orsonzhai@gmail.com, baolin.wang@linux.alibaba.com, zhang.lyra@gmail.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nadi Ke Subject: [PATCH v1 0/2] clk: sprd: Add support for Unisoc SC9832E clocks Date: Tue, 20 Jan 2026 22:44:34 +0800 Message-Id: <20260120144436.233998-1-kanadenady@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds the clock controller support for the Unisoc SC9832E SoC. The SC9832E is a quad-core ARM Cortex-A53 SoC from Unisoc (formerly Spreadtrum), widely used in entry-level smartphones. This series includes: 1. The device tree bindings in YAML format and its corresponding IDs. 2. The clock driver implementation based on the existing sprd common clock framework. The driver supports the following clock controllers: - PMU Gate, PLL, MPLL, DPLL, RPLL - AP AHB Gate, AON APB Gate, AP APB Gate - AP Clock, AON Clock Nadi Ke (2): dt-bindings: clock: sprd: Add SC9832E clock controller clk: sprd: Add SC9832E clock driver .../bindings/clock/sprd,sc9832e-clk.yaml | 129 ++ drivers/clk/sprd/Kconfig | 10 + drivers/clk/sprd/Makefile | 1 + drivers/clk/sprd/sc9832e-clk.c | 1065 +++++++++++++++++ include/dt-bindings/clock/sprd,sc9832e-clk.h | 187 +++ 5 files changed, 1392 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml create mode 100644 drivers/clk/sprd/sc9832e-clk.c create mode 100644 include/dt-bindings/clock/sprd,sc9832e-clk.h -- 2.34.1