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([223.74.152.156]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-352fb191a62sm507411a91.5.2026.01.20.23.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 23:14:55 -0800 (PST) From: Nadi Ke To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, orsonzhai@gmail.com, baolin.wang@linux.alibaba.com Cc: zhang.lyra@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nadi Ke Subject: [PATCH v2 0/2] clk: sprd: Add support for Unisoc SC9832E clocks Date: Wed, 21 Jan 2026 15:14:10 +0800 Message-Id: <20260121071412.256215-1-kenadicanady@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The SC9832E clock architecture involves several PLLs and gates. Some gate clocks are located within the PMU global register area. ** Author Email Change ** Please note that my previous email address (kanadenady@gmail.com) is no longer accessible. I am submitting this version from my new address (kenadicanady@gmail.com). I am the same author as the previous submission. Please update your records accordingly. ** Technical Details ** Based on the review comments from v1, I have significantly refactored the handling of the PMU gate clocks. The hardware registers for these gates are scattered within the PMU global register space (interleaved with other system controls) and do not form a contiguous region. To correctly model this hardware: 1. I removed the artificial child node (`sprd,sc9832e-pmu-gate`) which lacked a valid `reg` property. 2. The parent syscon node (`sprd,sc9832e-glbregs`) is now defined as the clock provider. 3. The driver has been updated to match the syscon compatible string directly. Verified on SC9832E hardware, clk_summary shows correct PLL rates and clock tree topology. Changes in v2: - dt-bindings: - Removed the artificial 'sprd,sc9832e-pmu-gate' child node definition. - Added '#clock-cells' to the 'sprd,sc9832e-glbregs' node definition. - Removed 'simple-mfd' from the parent node in the example to reflect that the child node (if present in dts) is logical and shares resources, or that the parent acts as the provider. - Simplified 'allOf' logic by merging similar conditions. - Added mock clock definitions in the example to fix dt_binding_check warnings. - Fixed 'compatible' array definition in the example to match schema. - clk driver: - Updated the OF match table to match 'sprd,sc9832e-glbregs' instead of the removed child node compatible string. - Fixed a compilation error due to a typo in variable names. - Updated Author email address. Nadi Ke (2): Add device tree bindings for Spreadtrum/Unisoc SC9832E clock controller. Add clock driver for Spreadtrum/Unisoc SC9832E SoC. .../bindings/clock/sprd,sc9832e-clk.yaml | 182 +++ drivers/clk/sprd/Kconfig | 10 + drivers/clk/sprd/Makefile | 1 + drivers/clk/sprd/sc9832e-clk.c | 1077 +++++++++++++++++ include/dt-bindings/clock/sprd,sc9832e-clk.h | 177 +++ 5 files changed, 1447 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml create mode 100644 drivers/clk/sprd/sc9832e-clk.c create mode 100644 include/dt-bindings/clock/sprd,sc9832e-clk.h -- 2.34.1