From: Ruidong Tian <tianruidong@linux.alibaba.com>
To: catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org,
guohanjun@huawei.com, sudeep.holla@arm.com, rafael@kernel.org,
robin.murphy@arm.com, mark.rutland@arm.com, tony.luck@intel.com,
bp@alien8.de, tglx@linutronix.de, peterz@infradead.org
Cc: lenb@kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org,
mchehab@kernel.org, xueshuai@linux.alibaba.com,
zhuo.song@linux.alibaba.com, oliver.yang@linux.alibaba.com,
Ruidong Tian <tianruidong@linux.alibaba.com>
Subject: [PATCH v6 05/16] ras: AEST: Probe RAS system architecture version
Date: Thu, 22 Jan 2026 17:46:45 +0800 [thread overview]
Message-ID: <20260122094656.73399-6-tianruidong@linux.alibaba.com> (raw)
In-Reply-To: <20260122094656.73399-1-tianruidong@linux.alibaba.com>
The RAS version of a component can be probed via its ERRDEVARCH register.
In cases where a component (e.g., SMMU) does not implement an ERRDEVARCH
register, the driver falls back to using the RAS version of the Processing
Element (PE).
Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>
---
arch/arm64/include/asm/ras.h | 3 +++
drivers/ras/aest/aest-core.c | 22 ++++++++++++++++++++++
drivers/ras/aest/aest.h | 3 +++
3 files changed, 28 insertions(+)
diff --git a/arch/arm64/include/asm/ras.h b/arch/arm64/include/asm/ras.h
index b6640b9972bf..da7c441252fe 100644
--- a/arch/arm64/include/asm/ras.h
+++ b/arch/arm64/include/asm/ras.h
@@ -4,6 +4,9 @@
#include <linux/types.h>
+/* ERRDEVARCH */
+#define ERRDEVARCH_REV GENMASK(19, 16)
+
struct ras_ext_regs {
u64 err_fr;
u64 err_ctlr;
diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c
index f4a5119dc513..84b2fb8127ff 100644
--- a/drivers/ras/aest/aest-core.c
+++ b/drivers/ras/aest/aest-core.c
@@ -16,6 +16,27 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev);
#undef pr_fmt
#define pr_fmt(fmt) "AEST: " fmt
+static int get_aest_node_ver(struct aest_node *node)
+{
+ u64 reg;
+ void *devarch_base;
+
+ if (node->type == ACPI_AEST_GIC_ERROR_NODE) {
+ devarch_base = ioremap(node->info->interface_hdr->address +
+ GIC_ERRDEVARCH,
+ PAGE_SIZE);
+ if (!devarch_base)
+ return 0;
+
+ reg = readl_relaxed(devarch_base);
+ iounmap(devarch_base);
+
+ return FIELD_GET(ERRDEVARCH_REV, reg);
+ }
+
+ return FIELD_GET(ID_AA64PFR0_EL1_RAS_MASK, read_cpuid(ID_AA64PFR0_EL1));
+}
+
static int aest_init_record(struct aest_record *record, int i,
struct aest_node *node)
{
@@ -108,6 +129,7 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node,
node->adev = adev;
node->info = anode;
node->type = anode->type;
+ node->version = get_aest_node_ver(node);
node->name = alloc_aest_node_name(node);
if (!node->name)
return -ENOMEM;
diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h
index 31131cce9928..bf0b9a49fdaa 100644
--- a/drivers/ras/aest/aest.h
+++ b/drivers/ras/aest/aest.h
@@ -61,6 +61,8 @@
#define ERXMISC2 0x30
#define ERXMISC3 0x38
+#define GIC_ERRDEVARCH 0xFFBC
+
struct aest_access {
u64 (*read)(void *base, u32 offset);
void (*write)(void *base, u32 offset, u64 val);
@@ -141,6 +143,7 @@ struct aest_node {
* error events.
*/
unsigned long *status_reporting;
+ int version;
const struct aest_group *group;
struct aest_device *adev;
--
2.51.2.612.gdc70283dfc
next prev parent reply other threads:[~2026-01-22 9:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-22 9:46 [PATCH v6 00/16] Support Armv8 RAS Extensions for Kernel-first error handling Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 01/16] ACPI/AEST: Parse the AEST table Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 02/16] ras: AEST: Add probe/remove for AEST driver Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 03/16] ras: AEST: support different group format Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 04/16] ras: AEST: Unify the read/write interface for system and MMIO register Ruidong Tian
2026-01-22 9:46 ` Ruidong Tian [this message]
2026-01-22 9:46 ` [PATCH v6 06/16] ras: AEST: Support RAS Common Fault Injection Model Extension Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 07/16] ras: AEST: Support CE threshold of error record Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 08/16] ras: AEST: Enable and register IRQs Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 09/16] ras: AEST: Add cpuhp callback Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 10/16] ras: AEST: Introduce AEST driver sysfs interface Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 11/16] ras: AEST: Add error count tracking and debugfs interface Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 12/16] ras: AEST: Allow configuring CE threshold via debugfs Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 13/16] ras: AEST: Introduce AEST inject interface to test AEST driver Ruidong Tian
2026-01-27 12:52 ` kernel test robot
2026-01-22 9:46 ` [PATCH v6 14/16] ras: AEST: Add framework to process AEST vendor node Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 15/16] ras: AEST: support vendor node CMN700 Ruidong Tian
2026-01-27 18:56 ` kernel test robot
2026-03-09 19:21 ` Robin Murphy
2026-03-13 9:49 ` Ruidong Tian
2026-01-22 9:46 ` [PATCH v6 16/16] trace, ras: add ARM RAS extension trace event Ruidong Tian
2026-03-09 13:28 ` [PATCH v6 00/16] Support Armv8 RAS Extensions for Kernel-first error handling Umang Chheda
2026-03-11 3:25 ` Ruidong Tian
2026-03-17 7:21 ` Umang Chheda
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