From: "Tomasz Pakuła" <tomasz.pakula.oficjalny@gmail.com>
To: alexander.deucher@amd.com, harry.wentland@amd.com, sunpeng.li@amd.com
Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org,
tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch,
siqueira@igalia.com, dri-devel@lists.freedesktop.org,
amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
tomasz.pakula.oficjalny@gmail.com, bernhard.berger@gmail.com,
michel.daenzer@mailbox.org, daniel@fooishbar.org
Subject: [PATCH v2 02/19] drm/amd/display: Refactor amdgpu_dm_update_freesync_caps()
Date: Sun, 25 Jan 2026 19:38:57 +0100 [thread overview]
Message-ID: <20260125183914.459228-3-tomasz.pakula.oficjalny@gmail.com> (raw)
In-Reply-To: <20260125183914.459228-1-tomasz.pakula.oficjalny@gmail.com>
[Why]
This function started to get very messy and hard to follow.
[How]
Eject some functionality to separate functions and simplify greatly.
Signed-off-by: Tomasz Pakuła <tomasz.pakula.oficjalny@gmail.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 119 +++++++++++-------
1 file changed, 72 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f01ddde1a50c..77a903880543 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -13098,8 +13098,8 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector,
}
}
-static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
- const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
+static int parse_amd_vsdb_did(struct amdgpu_dm_connector *aconnector,
+ const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
{
u8 *edid_ext = NULL;
int i;
@@ -13151,9 +13151,9 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
return false;
}
-static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
- const struct edid *edid,
- struct amdgpu_hdmi_vsdb_info *vsdb_info)
+static int parse_amd_vsdb_cea(struct amdgpu_dm_connector *aconnector,
+ const struct edid *edid,
+ struct amdgpu_hdmi_vsdb_info *vsdb_info)
{
u8 *edid_ext = NULL;
int i;
@@ -13183,6 +13183,44 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
return valid_vsdb_found ? i : -ENODEV;
}
+static bool is_monitor_range_invalid(struct drm_connector *conn)
+{
+ return conn->display_info.monitor_range.min_vfreq == 0 ||
+ conn->display_info.monitor_range.max_vfreq == 0;
+}
+
+/*
+ * Returns true if (max_vfreq - min_vfreq) > 10
+ */
+static bool is_freesync_capable(struct drm_monitor_range_info *range)
+{
+ return (range->max_vfreq - range->min_vfreq) > 10;
+}
+
+static void monitor_range_from_vsdb(struct drm_connector *conn,
+ struct amdgpu_hdmi_vsdb_info *vsdb)
+{
+ struct drm_monitor_range_info *range = &conn->display_info.monitor_range;
+
+ range->min_vfreq = vsdb->min_refresh_rate_hz;
+ range->max_vfreq = vsdb->max_refresh_rate_hz;
+}
+
+/*
+ * Returns true if connector is capable of freesync
+ * Optionally, can fetch the range from AMD vsdb
+ */
+static bool copy_range_to_amdgpu_connector(struct drm_connector *conn)
+{
+ struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
+ struct drm_monitor_range_info *range = &conn->display_info.monitor_range;
+
+ aconn->min_vfreq = range->min_vfreq;
+ aconn->max_vfreq = range->max_vfreq;
+
+ return is_freesync_capable(range);
+}
+
/**
* amdgpu_dm_update_freesync_caps - Update Freesync capabilities
*
@@ -13197,15 +13235,18 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
const struct drm_edid *drm_edid)
{
- int i = 0;
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
struct dm_connector_state *dm_con_state = NULL;
struct dc_sink *sink;
struct amdgpu_device *adev = drm_to_adev(connector->dev);
struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
+ struct amdgpu_hdmi_vsdb_info vsdb_did = {0};
+ struct dpcd_caps dpcd_caps = {0};
const struct edid *edid;
bool freesync_capable = false;
+ bool valid_vsdb_cea = false;
+ bool vsdb_freesync = false;
enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
if (!connector->state) {
@@ -13235,62 +13276,46 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
goto update;
edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
+ valid_vsdb_cea = parse_amd_vsdb_cea(amdgpu_dm_connector, edid, &vsdb_info) >= 0;
+ vsdb_freesync = valid_vsdb_cea && vsdb_info.freesync_supported;
+ if (amdgpu_dm_connector->dc_link)
+ dpcd_caps = amdgpu_dm_connector->dc_link->dpcd_caps;
/* Some eDP panels only have the refresh rate range info in DisplayID */
- if ((connector->display_info.monitor_range.min_vfreq == 0 ||
- connector->display_info.monitor_range.max_vfreq == 0))
+ if (is_monitor_range_invalid(connector))
parse_edid_displayid_vrr(connector, edid);
- if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
- sink->sink_signal == SIGNAL_TYPE_EDP)) {
- if (amdgpu_dm_connector->dc_link &&
- amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {
- amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
- amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
- if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
- freesync_capable = true;
- }
+ if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
+ sink->sink_signal == SIGNAL_TYPE_EDP) {
- parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
+ if (dpcd_caps.allow_invalid_MSA_timing_param)
+ freesync_capable = copy_range_to_amdgpu_connector(connector);
- if (vsdb_info.replay_mode) {
- amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
- amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
+ /* eDP */
+ if (edid)
+ parse_amd_vsdb_did(amdgpu_dm_connector, edid, &vsdb_did);
+
+ if (vsdb_did.replay_mode) {
+ amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_did.replay_mode;
+ amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_did.amd_vsdb_version;
amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
}
- } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
- i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
- if (i >= 0 && vsdb_info.freesync_supported) {
- amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
- amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
- if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
- freesync_capable = true;
-
- connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
- connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
- }
+ } else if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && vsdb_freesync) {
+ monitor_range_from_vsdb(connector, &vsdb_info);
+ freesync_capable = copy_range_to_amdgpu_connector(connector);
}
if (amdgpu_dm_connector->dc_link)
as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
- if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
- i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
- if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
+ if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST && vsdb_freesync) {
+ amdgpu_dm_connector->pack_sdp_v1_3 = true;
+ amdgpu_dm_connector->as_type = as_type;
+ amdgpu_dm_connector->vsdb_info = vsdb_info;
- amdgpu_dm_connector->pack_sdp_v1_3 = true;
- amdgpu_dm_connector->as_type = as_type;
- amdgpu_dm_connector->vsdb_info = vsdb_info;
-
- amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
- amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
- if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
- freesync_capable = true;
-
- connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
- connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
- }
+ monitor_range_from_vsdb(connector, &vsdb_info);
+ freesync_capable = copy_range_to_amdgpu_connector(connector);
}
update:
--
2.52.0
next prev parent reply other threads:[~2026-01-25 18:39 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-25 18:38 [PATCH v2 00/19] drm/amd: VRR fixes, HDMI Gaming Features Tomasz Pakuła
2026-01-25 18:38 ` [PATCH v2 01/19] drm/amd/display: Return if DisplayID not found in parse_amd_vsdb() Tomasz Pakuła
2026-01-25 18:38 ` Tomasz Pakuła [this message]
2026-01-25 18:38 ` [PATCH v2 03/19] drm/amd/display: Check for VRR range in CEA AMD vsdb Tomasz Pakuła
2026-01-25 18:38 ` [PATCH v2 04/19] drm/amd/display: Use bigger VRR range if found in " Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 05/19] drm/amd/display: Refactor PCON VRR compatibility check Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 06/19] drm/amd/display: Add PCON VRR ID check override Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 07/19] drm/amd/display: Add CH7218 PCON ID Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 08/19] drm/edid: Parse more info from HDMI Forum vsdb Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 09/19] drm/amd/display: Rename PCON adaptive sync types Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 10/19] drm/amd/display: Enable HDMI VRR over PCON Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 11/19] drm/amd/display: Support HDMI VRRmax=0 Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 12/19] drm/amd/display: Build HDMI vsif in correct slot Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 13/19] drm/amd/display: Save HDMI gaming info to edid caps Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 14/19] drm/amd/display: Restore ALLM support in HDMI vsif Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 15/19] drm/amd/display: Trigger ALLM if it's available Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 16/19] drm/amd/display: Add parameter to control ALLM behavior Tomasz Pakuła
2026-01-26 14:07 ` kernel test robot
2026-01-26 14:38 ` kernel test robot
2026-01-25 18:39 ` [PATCH v2 17/19] drm/amd/display: Reintroduce VTEM info frame Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 18/19] drm/amd/display: Enable HDMI VRR Tomasz Pakuła
2026-01-25 18:39 ` [PATCH v2 19/19] drm/amd/display: Add HDMI VRR desktop mode Tomasz Pakuła
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260125183914.459228-3-tomasz.pakula.oficjalny@gmail.com \
--to=tomasz.pakula.oficjalny@gmail.com \
--cc=airlied@gmail.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=bernhard.berger@gmail.com \
--cc=daniel@fooishbar.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=harry.wentland@amd.com \
--cc=linux-kernel@vger.kernel.org \
--cc=maarten.lankhorst@linux.intel.com \
--cc=michel.daenzer@mailbox.org \
--cc=mripard@kernel.org \
--cc=simona@ffwll.ch \
--cc=siqueira@igalia.com \
--cc=sunpeng.li@amd.com \
--cc=tzimmermann@suse.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®