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From: Breno Leitao <leitao@debian.org>
To: Thierry Reding <thierry.reding@gmail.com>,
	 Jonathan Hunter <jonathanh@nvidia.com>,
	 Sowjanya Komatineni <skomatineni@nvidia.com>,
	 Laxman Dewangan <ldewangan@nvidia.com>,
	Mark Brown <broonie@kernel.org>,  Vishwaroop A <va@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>,
	linux-tegra@vger.kernel.org,  linux-spi@vger.kernel.org,
	linux-kernel@vger.kernel.org,  Breno Leitao <leitao@debian.org>,
	kernel-team@meta.com, soto@nvidia.com
Subject: [PATCH v2 3/6] spi: tegra210-quad: Protect curr_xfer assignment in tegra_qspi_setup_transfer_one
Date: Mon, 26 Jan 2026 09:50:28 -0800	[thread overview]
Message-ID: <20260126-tegra_xfer-v2-3-6d2115e4f387@debian.org> (raw)
In-Reply-To: <20260126-tegra_xfer-v2-0-6d2115e4f387@debian.org>

When the timeout handler processes a completed transfer and signals
completion, the transfer thread can immediately set up the next transfer
and assign curr_xfer to point to it.

If a delayed ISR from the previous transfer then runs, it checks if
(!tqspi->curr_xfer) (currently without the lock also -- to be fixed
soon) to detect stale interrupts, but this check passes because
curr_xfer now points to the new transfer. The ISR then incorrectly
processes the new transfer's context.

Protect the curr_xfer assignment with the spinlock to ensure the ISR
either sees NULL (and bails out) or sees the new value only after the
assignment is complete.

Fixes: 921fc1838fb0 ("spi: tegra210-quad: Add support for Tegra210 QSPI controller")
Signed-off-by: Breno Leitao <leitao@debian.org>
---
 drivers/spi/spi-tegra210-quad.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index ee291b9e9e9c0..15c110c00aca5 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -839,6 +839,7 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
 	u32 command1, command2, speed = t->speed_hz;
 	u8 bits_per_word = t->bits_per_word;
 	u32 tx_tap = 0, rx_tap = 0;
+	unsigned long flags;
 	int req_mode;
 
 	if (!has_acpi_companion(tqspi->dev) && speed != tqspi->cur_speed) {
@@ -846,10 +847,12 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran
 		tqspi->cur_speed = speed;
 	}
 
+	spin_lock_irqsave(&tqspi->lock, flags);
 	tqspi->cur_pos = 0;
 	tqspi->cur_rx_pos = 0;
 	tqspi->cur_tx_pos = 0;
 	tqspi->curr_xfer = t;
+	spin_unlock_irqrestore(&tqspi->lock, flags);
 
 	if (is_first_of_msg) {
 		tegra_qspi_mask_clear_irq(tqspi);

-- 
2.47.3


  parent reply	other threads:[~2026-01-26 17:51 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-26 17:50 [PATCH v2 0/6] spi: tegra-qspi: Fix race condition causing NULL pointer dereference and spurious IRQ Breno Leitao
2026-01-26 17:50 ` [PATCH v2 1/6] spi: tegra210-quad: Return IRQ_HANDLED when timeout already processed transfer Breno Leitao
2026-01-26 17:50 ` [PATCH v2 2/6] spi: tegra210-quad: Move curr_xfer read inside spinlock Breno Leitao
2026-01-26 17:50 ` Breno Leitao [this message]
2026-01-26 17:50 ` [PATCH v2 4/6] spi: tegra210-quad: Protect curr_xfer in tegra_qspi_combined_seq_xfer Breno Leitao
2026-01-26 17:50 ` [PATCH v2 5/6] spi: tegra210-quad: Protect curr_xfer clearing in tegra_qspi_non_combined_seq_xfer Breno Leitao
2026-01-26 17:50 ` [PATCH v2 6/6] spi: tegra210-quad: Protect curr_xfer check in IRQ handler Breno Leitao
2026-01-30 10:16 ` [PATCH v2 0/6] spi: tegra-qspi: Fix race condition causing NULL pointer dereference and spurious IRQ Thierry Reding
2026-01-30 13:41   ` Jon Hunter
2026-01-30 17:07 ` Mark Brown

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