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Wed, 28 Jan 2026 03:40:51 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c642a9f41d0sm2010678a12.27.2026.01.28.03.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 03:40:50 -0800 (PST) From: Krishna Chaitanya Chundru Subject: [PATCH 0/3] PCI: qcom: Add D3cold support Date: Wed, 28 Jan 2026 17:10:40 +0530 Message-Id: <20260128-d3cold-v1-0-dd8f3f0ce824@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIALj1eWkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1NDIyNL3RTj5PycFN2kNEtLSyNDSzODpCQloOKCotS0zAqwQdGxtbUAwAp ahVgAAAA= X-Change-ID: 20251229-d3cold-bf99921960bb To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769600446; l=2654; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=kCxwBVLfjz8Zof/slL59vAhcEvihO5RxyP+2uMtSV3o=; b=1iPC8DVEc59rh8Oyk/lTBCt5bbqG+rgzg5oRfZjhYHR/NihEy8k0OzMXb8Thi5aaQ/SRGlKsP bbdS/jV/Ig+C94DjoNcBjWXw+F/lw3XTB0XWbQDQnBd8Or2pB88f/Dp X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: bX1ZSmmeMWLw-LPRjnl4X5GcfOaB1rbQ X-Authority-Analysis: v=2.4 cv=GbMaXAXL c=1 sm=1 tr=0 ts=6979f5c4 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=rF_suA9G3wk1FRvBKDEA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: bX1ZSmmeMWLw-LPRjnl4X5GcfOaB1rbQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI4MDA5NSBTYWx0ZWRfX8laK8oCXOiJ2 rUWN//XQjucc26WMycRanhSv+AwVa/48t9JH1WTfEh/TjR4OxZJkmfxt41DMeRrPA3skx9V1CnU vHq5iJ5d1aZBSXhq9dgOL6CMbHIGgqiXreQVrDFxHxnPBPLyKfg96Djt8CLVUsUtP7Rtrtwn3or wNAuyK8YYg3Z4Wi50lXxAc9zWGdp9Vo5E8UsgZzzhq2Jf+VIQlo0MuJu9Wz2Bh054KIW0LyeThV P30bFn5CwoaN4hSePekNpjjCH91dQ1yk7rqiG/R9ipgqXg9ACZoBFM1XB0x8nzRtPlTGVjbH87M WElXdIUsr2tbnxCMdI2CjMR73KOCI0qghj0nv1jF0j4EyJKh7GPAInW3kNiPA26YONAwtP4ds2r yhzgoraG3CAVTbustqhAG6J7+XOGUoAwNrjlySTRB5GbOx2z/IQeKoKjTc5x1asQwjXQ+IhO/+y Mj2p8NOg/yIaehS1EHA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_02,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601280095 This series adds a common helper to determine when a PCIe host bridge can safely enter D3cold, converts the DesignWare host driver to use that helper, and enables D3cold support for Qualcomm PCIe controllers. The first patch introduces pci_host_common_can_enter_d3cold() in pci-host-common. The helper walks all devices on the bridge's bus and only allows the host bridge to enter D3cold if all PCIe endpoints are already in PCI_D3hot. For devices that may wake the system, it additionally requires that the device support PME wakeup from D3cold (via WAKE#). Devices without wakeup enabled are not restricted by this check and may be left in D3cold. The second patch updates the DesignWare host driver to use this common helper in dw_pcie_suspend_noirq(). Previously, the driver skipped putting the link into L2 / device D3cold whenever L1 ASPM was enabled, since some devices (e.g. NVMe) expect low resume latency and may not tolerate deeper power states. However, such devices typically remain in D0 and are already covered by the helper's requirement that all endpoints be in D3hot before the host bridge may enter D3cold. Using the shared helper removes this coarse heuristic and centralizes the D3cold eligibility policy. The third patch enables D3cold support for Qualcomm PCIe controllers. It adds pme_turn_off() support and switches to the DesignWare common suspend/resume methods for device D3cold entry and exit. If the controller is not kept in D3cold, the existing paths are used so that ICC votes, OPP votes, and other resources remain managed as before. In addition, qcom_pcie_deinit_2_7_0() is updated to explicitly disable PCIe clocks and resets in the controller, and the now-unused "suspended" flag is removed from struct qcom_pcie. Signed-off-by: Krishna Chaitanya Chundru --- Krishna Chaitanya Chundru (3): PCI: host-common: Add shared D3cold eligibility helper for host bridges PCI: dwc: Use common D3cold eligibility helper in suspend path PCI: qcom: Add D3cold support drivers/pci/controller/dwc/pcie-designware-host.c | 7 +- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 114 +++++++++++++--------- drivers/pci/controller/pci-host-common.c | 29 ++++++ drivers/pci/controller/pci-host-common.h | 2 + 5 files changed, 101 insertions(+), 52 deletions(-) --- base-commit: 590a64365d9bcc13ee644a3e73ffdc3df26cf23c change-id: 20251229-d3cold-bf99921960bb Best regards, -- Krishna Chaitanya Chundru