From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F17EE2737E0 for ; Wed, 28 Jan 2026 18:11:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769623866; cv=none; b=FrbAg+wFDygmlB/1GKHMfHCu/NOiOuVKuoL9k9g0fe2ycDtRswwCMJZJuf9wUqerwx87LUYCCHXLkrK0/5n4UQvLKd1Y0fLNIKU+FnYXbe2zVtKWnfOsaF8sX9XdyVB2uLA1co+JaN549j8NuqCD3wAbBhiMCr+Oh/+Q8Xc4yw0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769623866; c=relaxed/simple; bh=EMvDSrhLuJYUdTt6x5YZzNaZ5Ae30vVVs3RJ1+GHQ7M=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=HCJIKz7Q7CWyYKnfayvy2Ri93ei2Iava4blYFovFhe4xqmVTyC1A6UuYy6DnJiOlxZFPqpVl5N1OGS8NXX42FjFJr1SRcN0mzuIwyxt7Hv7BrI2rXF9jPa69yv5m02tgZ3jgpzqmEEKv3hwTXme/DvFdhmCYlKQkTSij1oSkIDI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=qcq7Fqk8; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="qcq7Fqk8" Received: from killaraus.ideasonboard.com (2001-14ba-703d-e500--2a1.rev.dnainternet.fi [IPv6:2001:14ba:703d:e500::2a1]) by perceval.ideasonboard.com (Postfix) with UTF8SMTPSA id 5BD2C581; Wed, 28 Jan 2026 19:10:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1769623826; bh=EMvDSrhLuJYUdTt6x5YZzNaZ5Ae30vVVs3RJ1+GHQ7M=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qcq7Fqk8tFogFaa1gePWNLDgONDKPHtXc8LhrdeHuIYcKDJ0uGyg6M/PdJ4doFD/W FcXymOgG3nC9wZV5D1agQgOpocVMQARjvte5dR71hBImv/hMGmkAfFV/lTKkcvhkz5 XxNvyvFpPV7BQV3PQppY65gm2PoVHzjt4z+VzXiY= Date: Wed, 28 Jan 2026 20:11:01 +0200 From: Laurent Pinchart To: Tomi Valkeinen Cc: Vishal Sagar , Anatoliy Klymenko , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Michal Simek , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven , Dmitry Baryshkov , Pekka Paalanen Subject: Re: [PATCH v8 09/11] drm: xlnx: zynqmp: Add support for Y8 and Y10_P32 Message-ID: <20260128181101.GE3225981@killaraus> References: <20260128-xilinx-formats-v8-0-9ea8adb70269@ideasonboard.com> <20260128-xilinx-formats-v8-9-9ea8adb70269@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260128-xilinx-formats-v8-9-9ea8adb70269@ideasonboard.com> On Wed, Jan 28, 2026 at 07:25:34PM +0200, Tomi Valkeinen wrote: > Add support for Y8 and Y10_P32 formats. We also need to add new csc > matrices for the y-only formats. > > Reviewed-by: Vishal Sagar > Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart > --- > drivers/gpu/drm/xlnx/zynqmp_disp.c | 27 ++++++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c > index 1dc77f2e4262..57bb6d1dd10a 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c > @@ -307,6 +307,16 @@ static const struct zynqmp_disp_format avbuf_vid_fmts[] = { > .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10, > .swap = false, > .sf = scaling_factors_101010, > + }, { > + .drm_fmt = DRM_FORMAT_Y8, > + .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO, > + .swap = false, > + .sf = scaling_factors_888, > + }, { > + .drm_fmt = DRM_FORMAT_Y10_P32, > + .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10, > + .swap = false, > + .sf = scaling_factors_101010, > }, > }; > > @@ -697,6 +707,17 @@ static const u32 csc_sdtv_to_rgb_offsets[] = { > 0x0, 0x1800, 0x1800 > }; > > +/* In Y-only mode the single Y channel is on the third column */ > +static const u16 csc_sdtv_to_rgb_yonly_matrix[] = { > + 0x0, 0x0, 0x1000, > + 0x0, 0x0, 0x1000, > + 0x0, 0x0, 0x1000, > +}; > + > +static const u32 csc_sdtv_to_rgb_yonly_offsets[] = { > + 0x0, 0x0, 0x0 > +}; > + > /** > * zynqmp_disp_blend_set_output_format - Set the output format of the blender > * @disp: Display controller > @@ -846,7 +867,11 @@ static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp, > ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), > val); > > - if (layer->drm_fmt->is_yuv) { > + if (layer->drm_fmt->format == DRM_FORMAT_Y8 || > + layer->drm_fmt->format == DRM_FORMAT_Y10_P32) { > + coeffs = csc_sdtv_to_rgb_yonly_matrix; > + offsets = csc_sdtv_to_rgb_yonly_offsets; > + } else if (layer->drm_fmt->is_yuv) { > coeffs = csc_sdtv_to_rgb_matrix; > offsets = csc_sdtv_to_rgb_offsets; > } else { -- Regards, Laurent Pinchart